Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor...
Reexamination Certificate
2001-04-03
2002-06-25
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
C428S620000, C438S407000, C438S423000
Reexamination Certificate
active
06410938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to the manufacture of semiconductor devices, and in particular to methods of preventing dopant depletion in active regions of such devices.
2. Description of the Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, drain and source are located in a semiconductor substrate, with the channel being doped oppositely to the drain and source. The gate electrode is separated from the semiconductor substrate by a thin insulating layer (i.e., a gate dielectric layer) such as an oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET fabrication processes, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a mask. Other steps of IGFET fabrication processes, such as annealing, involve elevated temperatures.
During high temperature processing, dopant migration into buried oxide tends to occur. This dopant migration occurs at higher rates for dopant materials with low atomic weights, such as boron. As active surface semiconductor regions get increasingly thin, as in a fully-depleted SOI devices, the dopant migration can lead to undesirable front channel doping changes, as well as undesirable lowering of the threshold voltage of the unwanted back channel region.
SUMMARY OF THE INVENTION
A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. At least parts of the buried insulator layer include a nitrided semiconductor oxide. The nitrided semiconductor oxide may be formed by means of a nitride implant with sufficient energy to pass through a surface semiconductor layer and penetrate into a buried oxide layer. Following the nitride implant the device may be annealed to remove damage to the surface semiconductor layer, as well as to form a high quality nitrided oxide in the buried insulator layer. The nitrided semiconductor oxide material may reduce or prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.
According to an aspect of the invention, a semiconductor device includes a surface semiconductor region, and a buried nitrided semiconductor oxide layer underlying at least part of the surface semiconductor region.
According to another aspect of the invention, a method of making a semiconductor device includes the steps of: providing a semiconductor-on-insulator (SOI) wafer with a surface semiconductor layer and a buried insulator layer; implanting a nitrogen-containing material into the buried insulator layer through the surface semiconductor layer; and annealing the device to form a nitrided compound within the buried insulator layer.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 5468657 (1995-11-01), Hsu
patent: 5567638 (1996-10-01), Lin et al.
patent: 5629221 (1997-05-01), Chao et al.
patent: 5885877 (1999-03-01), Gardner et al.
patent: 6043138 (2000-03-01), Ibok
Advanced Micro Devices , Inc.
Booth Richard
Renner , Otto, Boisselle & Sklar, LLP
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