Abrading – Abrading process – Combined abrading
Reexamination Certificate
2000-10-20
2002-11-05
Wilson, Lee (Department: 3723)
Abrading
Abrading process
Combined abrading
C451S288000, C451S059000
Reexamination Certificate
active
06475069
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to polishing methods and slurry compositions or formulations that are used in polishing a semiconductor substrate having successive layers, comprised of, a metal layer, an underlying barrier or liner film, and an underlying dielectric layer having imbedded metal interconnect structures.
BACKGROUND OF THE INVENTION
Landers et al. in U.S. Pat. No. 5,676,587 discloses a two-step polishing process for polishing a semiconductor substrate. The first step utilizes CMP polishing with an alumina based slurry to remove a metal layer from an underlying barrier film. The second step utilizes CMP polishing with a silica-based slurry to remove the barrier film of Ta, TaN, Ti, or TiN. The silica-based slurry is pH neutral and is selective to Ta, TaN, Ti, or TiN to remove the barrier film.
While polishing a semiconductor substrate by CMP, it is critical to maintain the cross section and planarity of underlying conducting metal interconnect structures that provide metal circuit interconnect lines for a semiconductor structure, especially when polishing to attain high removal rates of the various layers. Excessive removal of the metal from the conducting metal lines is observed as cavities (known as “dishing”), which is undesirable, since optimal electrical performance is obtained when adequate metal for the conducting metal lines remains without being removed by polishing. Excessive removal of the SiO
2
dielectric layer within the underlying metal lines is observed as cavities (known as “erosion”), which is undesirable, since the dielectric layer should be flawless, free of cavities, adjacent to side geometry of the metal lines. Further, the polishing operation is required to polish the semiconductor substrate with a smooth planar polished surface on which are manufactured successive layers, which themselves are polished by CMP. Excessive dishing in the metal lines and excessive erosion in the dielectric layer comprise defects in the smooth planar polished surface.
A need exists for a method of polishing by CMP to attain high removal rates of both the metal layer and the barrier film, while minimizing dishing and erosion in the polished surface.
SUMMARY OF THE INVENTION
A method according to the invention provides a two step polishing process that includes, a first step of polishing a semiconductor substrate with a slurry composition selective to removal of copper during polishing, which removes a metal layer from an underlying barrier film, followed by a second step of polishing with a slurry formulation selective to removal of the barrier film and less selective to removal of copper, which removes the barrier film from an underlying dielectric layer and polishes the dielectric layer having copper metal lines therein with a smooth planar polished surface.
The method according to the invention further uses slurry compositions that are selective to removal of a metal in a metal layer during polishing of a semiconductor substrate by CMP, and a second slurry composition that is selective to removal of the barrier film, and less selective to removal of the metal providing metal lines in a dielectric layer that underlies the barrier film.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The invention provides a method of CMP polishing a semiconductor substrate having a metal layer, an underlying barrier film, and a dielectric layer having imbedded metal interconnect structures. This method is applicable to any metal interconnect structure containing: a conductive metal (such as Cu, Al, W, Pt, Pd, Au, or Ir), a barrier or liner layer (such as Ta, TaN, Ti, TiN, or TiW), and an underlying ILD structure (such as SiO
2
, TEOS, PSG, BPSG, or any low-K dielectric).
In an embodiment, polishing of a structure containing a Cu layer, an underlying Ta or TaN barrier layer, and a SiO
2
dielectric layer, using a two-step process is described. In the first step, the Cu overburden of excess metal is removed while removing minimal amounts of the Ta/TaN liner or SiO
2
. The slurry used in the first step of this process is one that can remove the copper metal overburden covering the semiconductor structure, and has very low rate of material removal on the Ta/TaN barrier film layer and underlying SiO
2
layer. Typically, this slurry would be alumina based, exhibit an acidic pH, and contain oxidizers that would enhance the chemical-mechanical removal of Cu at accelerated rates (above 2000 A/min).
For the second step suitable planarity has been obtained when using a slurry whose pH is basic and which gives the following range of removal rates for the various layers in the structure. These ranges may vary depending on the composition of the barrier layer and how it is formed, the metal layer and how it is formed, and the particular dielectric layer employed. Method 1 in Table A refers to a second step method trial that was performed, and shows high barrier removal rates while metal and dielectric removal rates remain low. Method 2 in Table A refers to a second step method trial that was performed, and shows high barrier removal rates while metal removal rates are moderate (between high and low) and a low dielectric removal rate.
TABLE A
TaN RR
Ta RR
Cu RR
SiO
2
RR
METHOD
(A/min)
(A/min)
(A/min)
(A/min)
1
>700
>400
<150
<250
2
>700
>400
<150-400
<250
The two methods trials of Table A have been found to give good planarity without significant dishing or erosion. Method trial 1 utilized a slurry that is selective to the barrier film and to high removal rates of Ta or TaN, and which is least selective to other materials, to provide the first method trial with desired minimized removal rates of both Cu and SiO
2
. This method trial should be used when an insignificant film of very little Cu overburden remains after first-step polishing. The Cu overburden is removed without significant polishing, and the slurry allows for rapid and complete removal of the Ta barrier layer, with low removal rate of CU such that there is significantly reduced removal of the Cu interconnect structures to minimize flaws produced by polishing. Further, slurry is selective to the SiO
2
with a higher selectivity than a minimized selectivity, such that the SiO
2
will be removed during second step polishing with a higher rate of removal than a minimized rate of removal, to become reduced in height to have a surface at the same level of the surface level of the Cu interconnect structures that have undergone dishing and concavity during first step polishing with a slurry with high selectivity to Cu that provides a high Cu removal rate.
The second method trial utilizes a slurry with significantly maximized or higher removal rates of Ta or TaN, and a minimized lower removal rate of SiO
2
. The slurry is selected for a selectivity for Cu that is higher than a minimized selectivity, to use when polishing to provide a corresponding higher rate of removal of CU than a minimized rate of removal of Cu, to remove spots of Cu that are present on the barrier film of Ta or TaN due to incomplete removal of the Cu by the first step polishing. This method should be used when some Cu overburden remains after stopping the first step polishing. This allows for the removal of any spots of Cu remaining on the wafer, complete and rapid removal of the Ta or TaN barrier layer, and minimized removal of the underlying SiO
2
layer to level the SiO
2
layer at the same level with a surface level of the interconnection structure.
With the proper application of the above methods, interconnect structures in semiconductor substrates can be produced with low observed dishing or recess of the interconnect structures (in particular, Cu) as well as low erosion of the underlying dielectric layer (i.e., SiO
2
). An advantage of these methods is that, the second step slurry is selected to compensate for any dishing, by selecting a slurry with an increased selectivity to SiO
2
, which removes the SiO
2
to the level of the Cu interconnect structures that have undergone dishing during the first step polishing. When the first s
Burke Peter A.
So Joseph K.
Thomas Terence M.
Ye Qianqiu (Christine)
Benson Kenneth A.
Kita Gerald K.
Rodel Holdings Inc.
Wilson Lee
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