Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-08-17
2002-02-26
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000, C323S316000
Reexamination Certificate
active
06351179
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and particularly, to a configuration and layout of a power supply circuit of the semiconductor integrated circuit which prevents a malfunction in a semiconductor integrated circuit caused by a transient change in power supply voltage when a power supply is turned on from occurring and suppresses a decrease in internal power supply voltage immediately after a transition from a stand-by mode to an active mode.
Conventionally, a power-on circuit has been known as a power supply voltage detecting circuit which generates a signal by detecting an increase and a decrease in power supply. When a power supply is turned on, a power supply voltage is increased and exceeds a preset value, a detection signal is generated and a prescribed latch in a semiconductor integrated circuit is reset to a required initial state using the signal. On the other hand, when a power supply voltage is decreased and reaches a preset value, a detection signal is generated, a prescribed latch is reset as in when a power supply is turned on. Then, description will be given of a necessity of resetting of a prescribed latch when a power supply voltage is decreased, taking a non-volatile memory having a floating gate as example.
A sectional view of a structure of a non-volatile memory cell is shown in FIG.
26
. Cells
1
and
2
are formed on a silicon substrate, wherein a control gate
40
and a floating gate
41
are provided to each of the cells
1
and
2
, channels are formed on the surface of a P well
42
and N-type diffusion layers
43
formed on the P well
42
are respectively used as a source and a drain.
A write operation of the non-volatile memory cell is effected by applying a high voltage of the order of 20V between the control gate
40
and the P well
42
with the control gate
40
being set positive. At this point, electrons are injected into the floating gate
41
from the P well
42
and the memory cell is in a written state.
Then, an erase operation is effected by applying a high voltage of the order of 20V between the control gate
40
and the P well
42
with a potential of the control gate
40
being set 0 or negative, contrary to the write operation, to draw back the electrons in the floating gate
41
injected in the write operation to the P well
42
. A situation in which the cell
1
is erased is shown in FIG.
26
.
That is, for example, when the cell
1
is selected on the assumption that the cells
1
and
2
of
FIG. 26
each are in a written state and if the control gate
40
and the P well are respectively applied with 0V and 20V, electrons (e
−
) injected in the floating gate
41
are drawn back to the P well
42
by a tunnel effect to have the cell
1
to be an erased state.
At this point, the control gate
40
is applied with 20V in a non-selected cell
2
and no potential difference between the floating gate
41
and the P well
42
arises. Therefore, electrons injected in the floating gate
41
of the cell
2
are retained.
However, in a case where a power supply voltage is decreased in the erase operation for some reason, a logic circuit malfunctions due to the voltage decrease and in turn, a voltage of the control gate
40
of the cell
2
is decreased to 0V although the voltage should normally be applied with 20V. With the decrease in the voltage, electrons in the floating gate
41
of the cell
2
which should normally be retained are drawn back to the P well
42
, thereby effecting an erroneous erase operation.
In order to prevent such a malfunction, it is indispensable that a decrease in power supply voltage is detected immediately when it arises and a potential of the P well
42
be decreased from 20V to 0V. A power-on signal to be generated when the power supply voltage is decreased is necessary for such a recovery operation.
Conventionally, as a circuit which generates a power-on signal, a power supply voltage detecting circuit as shown in
FIG. 27
has been employed. The power supply voltage detecting circuit of
FIG. 27
is constructed of: a power supply; resistors R
1
, R
2
and R
3
; an N channel MOS transistor (hereinafter referred to as NMOS) M
1
with a threshold voltage Vtn; a P channel MOS transistor (hereinafter referred to as PMOS) M
2
with a threshold voltage Vtp; a node N
1
connecting a connection point between the resistors R
1
and R
2
and the gate of PMOS (M
2
) with each other; a node N
2
connecting the drain of PMOS (M
2
) and the resistor R
3
; and two inverters
15
and
16
connected to the output side. A power supply voltage and a voltage of the node N
1
when a power supply is turned on are respectively denoted by V and VN
1
, then VN
1
is given as follows:
VN
1
=R
1
×Vtn/(R
1
+R
2
)+R
2
×V/(R
1
+R
2
) (1)
In a case where, when a power supply is turned on, a difference between V and VN
1
exceeds the absolute value |Vtp| of a threshold voltage of PMOS (M
2
), that is, when the power supply voltage is higher than Vpwon, which is expressed as follows:
Vpwon=Vtn+|Vtp|×(R
1
+R
2
)/R
1
(2)
a potential of the node N
2
goes to high level (hereinafter expressed as “H”) and an output of the power-supply detecting circuit changes to “H” from a low level (hereinafter referred to as “L”). With this operation adopted, a prescribed latch in a semiconductor integrated circuit can be reset. When a power supply voltage is decreased and reaches the level of the equation (2), the output changes from “H” to “L” and the prescribed latch can be reset.
Incidentally, in
FIG. 27
, the gate and drain of NMOS (M
1
) are connected with each other and used as an NMOS connected as a diode. Further, the resistor R
2
may be removed in the circuit shown in
FIG. 27
since no problem occurs even if the resistance R
2
=0 in the equations (1) and (2).
The power supply voltage detecting circuit is employed in a circuit system in which no down converter is provided. In a circuit system in which an external power supply voltage Vext is decreased to an internal power supply voltage Vint using a down converter, a configuration and function of the power supply voltage detecting circuit is more or less altered.
The down converter system used herein (see “Super LSI memory,” authored by Shizuo ITO published by BAIFU KAN, p 267) is a circuit system in which Vext (for example, 3V) which is supplied from the outside of a semiconductor chip is decreased to Vint (for example, 2.5V) using a down converter and the Vint is used as a power supply for an internal circuit in the semiconductor integrated circuit.
A down converter system is especially widely used in semiconductor integrated circuits such as a memory and is useful as a very effective measure to cope with reduction in breakdown voltage of a transistor used in an internal circuit, which accompanies progress in microfabrication technique, and further, becomes an important measure to support a trend toward a multiple power supply for a semiconductor integrated circuit.
In a down converter system, two kinds of power supply detecting circuits for Vext and Vint are required. A Vext detecting circuit detects an increase in Vext and activates a down converter and a reference voltage (hereinafter referred to as Vref) generating circuit, while, when Vext is decreased, the circuit provides a function similar to a conventional manner.
A Vint detecting circuit further functions to reset a latch to a required initial condition in an increase in Vint as in a conventional manner when a power supply is turned on. However, when Vint is decreased, the Vint detecting circuit is not required to output a signal. The reason why is that the Vext detecting circuit detects a decrease in external power supply voltage prior to a decrease in internal power supply voltage Vint.
If functions of the Vext and Vint detecting circuits are considered, it is understood that a detecting circuit which outputs signals when a power supply voltage reaches
Ikehashi Tamio
Imamiya Kenichi
Iwata Yoshihisa
Sugiura Yoshihisa
Takeuchi Ken
Banner & Witcoff , Ltd.
Cunningham Terry D.
Kabushiki Kaisha Toshiba
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