Semiconductor circuit with a stabilized gain slope

Details Semiconductor circuit with a stabilized gain slope Semiconductor circuit with a stabilized gain slope

2001-08-22

2002-11-05

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including frequency-responsive means in the signal...

C330S294000, C330S310000, C330S098000

Reexamination Certificate

active

06476679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit, and particularly to a semiconductor circuit used in CATV (CAble TeleVision) hybrid IC (HIC).
2. Description of the Related Art
In HIC (hybrid IC) broadband amplifiers for CATV, a plurality of stages of amplifiers are connected in series via coaxial cable, and a desired gain slope must be established across the entire employed frequency band to correct for characteristic lost in the coaxial cable. Gain slope is such that gain increases with higher frequencies within the bandwidth.
Realization of desired gain slope in the frequency bands employed has become more difficult in recent years as the frequency bandwidths that are used have extended to higher frequencies.
FIG.
1
and
FIG. 2
are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Utility Model laid-open application No. 85810/83.
In the circuits shown in FIG.
1
and
FIG. 2
, a parallel resonant circuit is formed by inductor L
101
, which is provided in a bias feedback circuit, and capacitor C
102
, which is provided between the base and emitter of transistor Tr
101
. In addition, damping resistor R
106
connected in a series with capacitor C
102
between the base and emitter of transistor Tr
101
is provided to control Q in the resonant circuit.
In a circuit configured according to the foregoing description, the resonance frequency is altered by changing the element constants of inductor L
101
and capacitor C
102
, thereby regulating the peaking frequency.
FIG.
3
and
FIG. 4
are circuit diagrams showing the configuration of circuits for realizing a desired gain slope used in the prior art as disclosed in Japanese Patent Laid-open No. 264404/89.
In the circuit shown in
FIG. 3
, a serial resonant circuit is formed by capacitor C
112
and inductor L
111
in an interstage circuit provided between two amplifier circuits, and in the circuit shown in
FIG. 4
, FET(Field Effect Transistor) Tr
113
is provided such that inductor L
111
is connected in parallel between the source and drain, and a parallel resonant circuit is formed by inductor L
111
and the capacitance between the source and drain of FET Tr
113
.
In the circuits configured according to the foregoing description, alteration of resonance frequency is realized by changing the gate bias to vary the capacitance between the source and drain of FET Tr
113
, thereby regulating peaking frequency.
However, the above-described circuits of the prior art have the following drawbacks:
(1) In the circuits shown in FIG.
1
and
FIG. 2
, resonance frequency is altered by changing the element constants of inductor L
101
and capacitor C
102
to regulate the peaking frequency, but the impedance on the input side and output side change according to the amount of peaking because inductor L
101
and capacitor C
102
are provided in the feedback circuit.
The resulting circuit therefore has the three factors of input and output impedance and gain slope, and design and adjustment consequently require considerable time and trouble.
(2) In the circuits shown in FIG.
3
and
FIG. 4
, the resonance frequency is changed and the peaking frequency adjusted by changing the gate bias to change capacitance between the source and drain of the FET, and these circuits therefore require a variable bias to allow change of the gate bias. These circuits also require the additional provision of an FET. As a result both the scale and cost of the circuit is increasing.
(2) In the circuits shown in FIG.
3
and
FIG. 4
, the resonance frequency is changed and the peaking frequency adjusted by changing the gate bias to change capacitance between the source and drain of the FET, and these circuits therefore require a variable bias to allow change of the gate bias. These circuits also require the additional provision of a FET. As a result both the scale and cost of the circuit increases.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor circuit that can realize a stable gain slope without increasing the circuit scale or necessitating extra time for correcting impedance.
In this invention, a resonant circuit is provided outside a feedback loop for effecting peaking at a particular frequency and for realizing a gain slope having a desired inclination, for example, an inclination of 1 dB or more. As a result, the oscillation operation need not be considered when designing the circuit.
In addition, in a case in which a resonant circuit is provided in the output stage of a feedback loop, change in impedance occurs only on the output side and change in impedance does not occur on the input side. A circuit can therefore be designed and adjusted while considering only two factors and without taking the input side into consideration, thereby facilitating adjustment.
Finally, the invention does not entail enlargement of circuit scale because additional active elements are not necessary.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.


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