Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-12-30
2002-10-08
Willie, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S390000
Reexamination Certificate
active
06462363
ABSTRACT:
FIELD
The present invention generally relates to compact, stacked layer configurations for integrated circuits, which allow programmability on each layer.
BACKGROUND
Although a ROM (read-only-memory) cell and a version number associated with an IC (integrated circuit) will be used to describe examples of both the background and the invention, practice of the present invention is not limited to the same.
Turning first to a background,
FIG. 1
illustrates a portion of an integrated circuit IC
1
. Often ICs include groups of ROM cells which are pre-programmed during IC design, with such preprogramming propagating through manufacturing, to provide desired values or code. For example, in
FIG. 1
, IC
1
has an example plurality of ROM cells C
A
, C
B
, C
C
, C
D
, . . . , having outputs O
A
, O
B
, O
C
, O
D
, . . . , respectively. Each ROM cell may have a selectably programable physical arrangement which can be arranged during IC design and/or manufacturer, so as to program the ROM cell to output a desired value. For example,
FIG. 2
shows an example cross-section of an example ROM cell C
n
.
Such ROM cell is typically formed of a plurality of layers, for example, the ROM cell C
n
may have layers L
A
, L
B
, L
C
, L
D
, and some of the layers may be electrically interconnected with other layers using vias layers V. The layers L
A
, L
B
, L
C
, L
D
may be any of a plurality of different types, for example, semiconductor well, diffusion, polysilicon, contacts, metal conductor, vias, etc. constructions, with such layers being resultant from a plurality of different masks (and other processes) applied during IC manufacturing. One of such layers may have the above-discussed selectably programmable portion P, i.e., so as to be selectably programmable during IC design and/or manufacture so as to configure or program the ROM cell according to at least two possible choices, e.g., to output a logical “1” or logical “0”, a first voltage level Vcc or a second voltage level Vss, etc.
As one example of a use of groups of ROM cells on an IC, often times after IC manufacturing, numerous different versions, generations or lots (hereinafter, “versions”) of an IC chip will be design modified (e.g., improved) and/or modified during manufacturing in a strive to remove paracitics and/or unwanted behavior and/or improve performance, e.g., often by changing a layout of one or more masks which were used to pattern the IC from one version to another. During subsequent analysis/comparison of the differing version IC chips, often it becomes important to be able to determine to which version a particular IC chip belongs. Accordingly, in order to meet such need, the outputs O
A
, O
B
, O
O
, O
D
, . . . , of the
FIG. 1
example plurality of ROM cells C
A
, C
B
, C
C
, C
D
, . . . , respectively, could be programmed (i.e., constructed) during design and/or manufacture to output a version number of the IC, e.g., to output a binary value of “0001” for a first version IC, a binary value of “0010”for a second version IC, etc. If desired, such outputs from the ROM cells could then be accessed during analysis/comparison to determine to which version a particular chip belongs.
In addition, several differing groups of ROM cells could be used to separately provide differing information, for example, a first group of ROM cells could be used to provide a unique serial number for the IC chip, a second group could be used to identify the exact masks used for a first type of layer (e.g., metal layer), a third group could be used to identify the exact masks used for a second type of layer, another group could be used to identify a date or manufacturing plant of manufacture. Such information could then be used for IC chip identification purposes, or for verification purposes, e.g., to check to see if the proper sets of masks were used.
Discussion turns next to disadvantages with the
FIGS. 1-2
arrangement. More particularly, a first disadvantage with the
FIGS. 1-2
arrangement is that such ROM cells are not programmable at each layer. More particularly, assume that after analysis of a first version IC, it is determined that a configuration of the
FIG. 2
layer L
B
should be changed in order to remove a paracitics and/or unwanted behavior and/or improve performance. Accordingly, a mask used to produce this layer L
B
may be changed. Since any IC manufactured with this changed mask would represent a new version IC, the version number programmed within the ROM cells C
A
, C
B
, C
C
, C
D
, . . . , should also be changed. However, since the programmable portions P of the ROM cells are not within the layer L
B
and instead are within layer L
D
, a mask for the programmable layer L
D
must also be changed in order to change the IC version number. The required change of two masks instead of just one is a disadvantage in terms of increased manufacturing complexity, costs and increased time-to-market (TtM) delays.
As a second disadvantage, a size of the programmable portion P may be larger than other arrangements within the ROM cell and may increase a size of each ROM cell, such that the ROM cells C
A
, C
B
, C
C
, C
D
, . . . , have substantial wasted die space W (
FIG. 1
) therebetween. Wasted die space is incompatible with present day trends toward increased miniaturization and lowered IC costs, and therefore is disadvantageous.
SUMMARY
The invention is directed to a programmable IC (integrated circuit) arrangement. Included are: at least one input/output terminal; at least two receiver/source terminals for selectable electrical connection to the at least one input/output terminal; and a plurality of layers electrically interconnected with one another and providing electrical connection between the at least one input/output terminal and at least one of the at least two receiver/source terminals. At least a sub-plurality of the plurality of layers includes electrically conductive components selectably providable at at least two positions so as to selectably program electrical connection between the at least one input/output terminal and the at least two receiver/source terminals.
REFERENCES:
patent: 4352031 (1982-09-01), Holbrook et al.
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Louie Wai-Sing
Willie Douglas A.
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