Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2000-09-08
2002-10-08
Riley, Shawn (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
C363S131000, C363S041000, C363S055000
Reexamination Certificate
active
06462962
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of switching DC-to-DC power conversion and in particular to the new class of switching converters employing novel type of lossless switching which provides simultaneously the ultra high efficiency in a very compact size and additional performance advantages, such as much reduced EMI noise and much improved reliability.
BACKGROUND OF THE INVENTION
Definitions and Classifications
The following notation is consistently used throughout this text in order to facilitate easier delineation between various quantities:
1. DC—Shorthand notation historically referring to Direct Current but by now has acquired wider meaning and refers generically to circuits with DC quantities;
2. AC—Shorthand notation historically referring to Alternating Current but by now has acquired wider meaning and refers to all Alternating electrical quantities (current and voltage);
3. i
1
, v
2
—The instantaneous time domain quantities are marked with lower case letters, such as i
1
and v
2
for current and voltage;
4. I
1
, V
2
—The DC components of the instantaneous periodic time domain quantities are designated with corresponding capital letters, such as I
1
and V
2
,
5. &Dgr;i
1
—The difference between instantaneous and DC components is designated with &Dgr;, hence &Dgr;i
1
designates the ripple component or AC component of current i
1
;
6. D—The duty ratio of the input switch S
1
is defined as D=t
ON
/T
S
where t
ON
is ON time of the input switch, and T
S
is the switching period defined as T
S=
1/f
S
where f
S
is a constant switching frequency. Switch S
1
is closed and conducts current (turned ON) during DT
S
interval;
7. D′—The complementary duty ratio D′ of the input switch S
1
is defined as D′=1−D and D′T
S
is interval during which input switch S
1
is open (turned OFF);
8. S
1
, S
2
, S′
1
, S′
2
—Switch designations respectively for input switch, output switch, complementary input switch, and complementary output switch and, at the same time, designate the switching states of the respective active, controllable switches as follows: high level indicates that active switch is turned ON, low (zero) level that it is turned OFF;
9. CR
1
—Designation for the current rectifier (CR) diode and its corresponding switching time diagram. Since diode is a two-terminal passive switch, switching time diagram represents also the state of diode switch as follows: high level indicates that the diode is ON and low level that it is OFF;
10. I—One quadrant switch is designated by Roman number (I through IV) within a rectangular box around ideal switch signifying its limitation to particular one-quadrant operation;
11. CBS—Designates the Current Bi-directional Switch as a three-terminal controllable semiconductor switching device, which conducts the current in either direction in an ON-state, but blocks the voltage of only one polarity in an OFF-state between two power terminals and has a third controlling terminal to independently control the state of the switch between two power terminals;
12. VBS—Designates the Voltage Bi-directional Switch as a three-terminal controllable semiconductor switching device, which conducts the current in only one direction in the ON-state, but blocks the voltage of either polarity in an OFF-state between the two power terminals and has a third controlling terminal to independently control the state of the switch between two power terminals;
13. CBS/VBS—Designates that either Current Bi-directional Switch (CBS) or Voltage Bi-directional Switch (VBS) can be used.
The demand for reduced size and weight of electronic power processing equipment to make it compatible with ever shrinking size of electronic signal processing equipment resulted in the continuous push toward increasing the switching frequency at which DC-to-DC switching converters operate: from initial 20 kHz level to 200 kHz and higher switching frequencies. This, in turn, results in proportionally increased switching power losses. Hence, in the past, a number of converter topologies have emerged, which belong to two broad categories:
1. Hard-switching converter category in which no attempts were made to reduce the switching losses;
2. Soft-switching converter category in which measures were taken to reduce the switching losses.
Unfortunately, in most cases, the reduction of switching losses was accompanied with the increase of other losses, such as conduction losses of the switching devices or losses associated with energy stored in transformer leakage inductance and other additional losses, which resulted only in small to moderate improvements in efficiency.
The switching converters can also be classified into three classes relative to a number of switches employed:
1. Two-Switch Converter class, example of which is the prior-art buck converter.
2. Three-Switch Converter class such as prior-art forward converter;
3. Four-Switch Converter class such as the present invention and a number of other prior-art converters.
Prior-Art Soft-Switching Converters
One of the first soft-switching methods which provided reduction of switching losses was introduced by C. Henze, H. C. Martin and D. W. Parsley in “Zero-Voltage Switching in High-Frequency Power Converters Using Pulse-Width Modulation”,
IEEE Applied Power Electronics Conference
, (IEEE Publication 88CH2504-9) pp33-40, 1988 record on a basic buck converter which belongs to Two-Switch Converter class and is shown in prior-art of FIGS.
1
(
a-g
).
In order to obtain zero-voltage switching at a constant switching frequency, the usual transistor-diode implementation of two switches is replaced with two MOSFET transistors, each of which is modeled as a parallel connection of an ideal switch with an anti-parallel “body” diode and a parasitic drain-to-source capacitor, resulting in circuit models of FIGS.
1
(
c-f
). The total switching cycle T
S
is broken down into 4 intervals by proper drive timing of the two switches S and S′ as shown in
FIG. 2
e
. Note that with two controllable switches, two well defined transition intervals are introduced during which both switches are OFF. The first transition interval (t
N
in
FIG. 2
e
), starts when switch S is turned OFF (as in
FIG. 2
e
) and is also known as the “natural” transition (DT
S
to D′T
S
transition, or simply D to D′ transition). By turning OFF the switch S, the inductor current I
P
is flowing naturally in a needed direction (represented by the current source I
P
on
FIG. 2
a-f
). This current source I
P
charges the parasitic capacitor C
S
of switch S and discharges parasitic capacitor C′
S
of switch S′ until capacitor C′
S
is fully discharged at which instant the body-diode of switch S′ clamps the voltage at zero and prevents reverse charging of capacitor C′
S
of switch S′. At that instance, the switch S′ can be turned ON with zero switching losses (
FIG. 2
e
), since the charge of C′
S
was already relocated to capacitance C
S
of the switch S (charged to V
g
). In order to perform the reverse process during the D′ to D transition, a negative inductor current I
N
is needed. The simplest method to accomplish this is to design the output inductor to have a large ripple current, such that its peak-to-peak ripple current is at least 3 times the maximum DC load current. As seen in the inductor current waveform in
FIG. 2
e
, the instantaneous inductor current i
L
will at some point during D′T
S
interval reverse direction and become negative with magnitude I
N
. Just before the end of complementary interval D′T
S
the switch S′ is turned OFF initiating the so-called “forced” transition (since the inductor current is now intentionally forced to become negative by the converter circuit designed for large ripple). During this forced transition interval (t
F
in
FIG. 2
e
), the opposite to t
N
interval occurs: this negative inductor current I
N
charges parasitic capacitor C′
S
of switch S′ an
Fernandez A. M.
Riley Shawn
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