Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-08-08
2002-12-03
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S145000
Reexamination Certificate
active
06489905
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to digital-to-analog converters and in particular the present invention relates to calibrating digital-to-analog converters (DAC).
BACKGROUND OF THE INVENTION
Digital-to-analog (D/A) conversion is the process of converting digital codes into a continuous range of analog signal levels. Major factors that determine the quality of performance of DACs are resolution, sampling rate, speed, and linearity. Generally, the accuracy of the DAC's measurement and conversion is specified by the converter's linearity. “Integral linearity” is a measure of linearity over the entire conversion range. It is defined as the deviation from a straight line drawn between the maximum point and through zero (or the offset value) of the conversion range. “Differential linearity” is the linearity between adjacent steps of the analog output. Differential linearity is a measure of the monotonicity of the converter. The converter is said to be monotonic if increasing input values result in increasing output values.
Digital codes are typically converted to analog voltages by assigning a voltage weight, or current weight, to each bit in the digital code and summing the voltage or current weights of the entire code. This type of DAC is called a binary weighted DAC. DACs that produce analog current outputs usually have a faster settling time and better linearity than those that produce a voltage output.
As is well known in the art, a “segmented” DAC design converts digital codes to analog signals by activating a number of weighted segments proportional to the input digital code and summing the activated segments to form the analog output signal.
Identical segments improve differential linearity by a considerable amount over a straight binary weighted implementation; however, process tolerances are generally too large to achieve the integral linearity requirements of modern high performance digital to analog converters. See U.S. Pat. No. 5,666,118, issued Sep. 9, 1997 to Gersbach and entitled “Self calibration segmented digital-to-analog converter” for description of a self-calibrating DAC. Another self-calibrating DAC is described in U.S. Pat. No. 5,446,455, issued Aug. 29, 1995 to Brooks and entitled “Auto-Calibrated Current-Mode Digital-to-Analog Converter and Method therefor”. See also U.S. Pat. No. 5,955,980, issued Sep. 21, 1999 to Hanna and entitled “Circuit and Method for Calibrating a Digital-to-Analog Converter”.
In non-segmented DACs, reference current sources can be calibrated using a “golden” current source to improve accuracy. In segmented DACs, two or more reference currents of appropriate ratio dictated by the percentage of segmentation are required to calibrate the current sources in each segment. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved circuit and method for calibrating segmented DACs.
SUMMARY OF THE INVENTION
The above-mentioned problems with digital to analog converters and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a segmented digital to analog converter (DAC) circuit comprises a plurality of sub-DACs to receive digital input signals and provide an analog output. The plurality of sub-DACs each comprises current source circuits. A reference generator circuit provides calibration currents to each of the plurality of sub-DACs, and a primary calibration current source is coupled to the reference generator circuit to calibrate the calibration currents for each of the plurality of sub-DACs.
In another embodiment, a segmented digital to analog converter (DAC) circuit comprises first, second and third sub-DACs to receive digital input signals and provide an analog output. The first, second and third sub-DACs each comprise current source circuits that comprise a sourcing current source, and a transistor coupled in parallel to the sourcing current source. The gate of the transistor is coupled to the drain to receive a voltage such that the sourcing current source and the transistor conduct a sum current equal to a calibration current. A reference generator circuit provides calibration currents to each of the first, second and third sub-DACs, and a primary calibration current source coupled to provide a I
unit
current to the reference generator circuit to calibrate the calibration currents for each of the first, second and third sub-DACs.
In yet another embodiment, a 10-bit segmented digital to analog converter (DAC) circuit comprises a first sub-DAC to convert two least significant digital inputs into a first analog current. The first sub-DAC comprises a first decoder and a plurality of first current sources each providing a current of 1×. A second sub-DAC converts four intermediate digital inputs into a second analog current. The second sub-DAC comprises a second decoder and a plurality of second current sources each providing a current of 4×. A third sub-DAC converts four most significant digital inputs into a third analog current. The third sub-DAC comprises a third decoder and a plurality of third current sources each providing a current of 64×. A reference generator circuit provides calibration currents of 4×, 4× and 64× to the first, second and third sub-DACs, respectively. A primary calibration current source coupled to the reference generator circuit provides a primary calibration current of 4× to calibrate the 4× and 64× calibration currents.
A method of calibrating a segmented digital to analog converter (DAC) circuit comprises providing a master calibration current, calibrating a plurality of reference currents using the master calibration current, coupling each of the plurality of reference currents to respective DAC segments, and calibrating current sources of the DAC segments using the plurality of reference currents.
Another method of calibrating a three-segmented 10-bit digital to analog converter (DAC) circuit comprises providing a master calibration current, calibrating a first and second reference currents using the master calibration current, coupling each of the first and second reference currents to first and second DAC segments, and calibrating current sources of the first and second DAC segments using the first and second reference currents.
REFERENCES:
patent: 5446455 (1995-08-01), Brooks
patent: 5666118 (1997-09-01), Gersbach
patent: 5703586 (1997-12-01), Tucholski
patent: 5955980 (1999-09-01), Hanna
patent: 6329941 (2001-12-01), Farooqi
Bastos et al., A 12-Bit Intrinsic Accuracy HIgh-Speed CMOS DAC,IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1959-1969.
Hassoun Marwan M.
Lee Yvette P.
Fogg Slifer & Polglaze
Williams Howard L.
Xilinx , Inc.
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