Photoelectric conversion devices and photoelectric...

Details Photoelectric conversion devices and photoelectric... Photoelectric conversion devices and photoelectric...

2000-12-04

2002-11-19

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S292000, C257S348000

Reexamination Certificate

active

06483163

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to photoelectric conversion devices and photoelectric conversion apparatus employing such photoelectric conversion devices. More particularly, the invention pertains to photoelectric conversion devices and photoelectric conversion apparatus designed both for high production yield, even in apparatus with large numbers of pixels, and for increased performance, such as increased signal-to-noise ratio and increased sensitivity, particularly to longer wavelengths.
BACKGROUND
Amplifying photoelectric conversion devices increase the sensitivity of the photoelectric conversion process by amplifying, within each pixel, the signal generated by each pixel.
FIGS. 45 through 48
are schematic diagrams showing a conventional photoelectric conversion device, as disclosed in Ishida et al., “The Development of 1.6 Million-pixel Amplification Type Image Sensor BCAST,”
The Journal of the Institute of Image Information and Television Engineers
(
Japan
), Vol. 51, No. 2, pp. 211-218 (1997).
FIG. 45
is a plan view;
FIG. 46
is a cross-sectional view taken along the X
1
-X
2
line shown in
FIG. 45
;
FIG. 47
is a cross-sectional view taken along the Y
1
-Y
2
line of
FIG. 45
; and
FIG. 48
is a cross-sectional view taken along the Y
3
-Y
4
line of FIG.
45
.
As shown in
FIGS. 45 through 48
, this conventional photoelectric conversion device includes a photodiode
1
for generating and accumulating an electric charge (hereinafter referred to simply as a charge) in response to incident light. A junction field-effect transistor (JFET)
2
receives (at the gate region thereof) the charge from the photodiode
1
and amplifies and outputs the charge. A transfer gate
3
transfers the charge generated and accumulated in the photodiode
1
to the gate region of the JFET
2
. A reset drain
4
controls the electric potential of the gate region of the JFET
2
. A reset gate
5
controls the electrical connection between the gate region of the JFET
2
and the reset drain
4
.
The photodiode
1
, the JFET
2
, and the reset drain
4
are formed in an N-type well region
11
formed on a P-type semiconductor substrate
10
. The transfer gate
3
and the reset gate
5
are formed above the N-type well region
11
, separated from the N-type well region
11
by an insulating film.
As shown in
FIGS. 47 and 48
, the photodiode
1
has a P-type charge-accumulation region
12
formed in the N-type well region
11
on the P-type semiconductor substrate
10
, and a high-density N-type semiconductor layer
13
formed on the P-type charge-accumulation region
12
and near the top surface of the semiconductor. Thus, a buried photodiode having an NPNP vertical overflow drain structure (or more precisely, an NPN buried photodiode, and a PNP overflow drain) is formed, as considered in the direction from the semiconductor surface toward the semiconductor substrate
10
. The JFET
2
has a P-type gate region
15
formed in the N-type well region
11
. The JFET
2
also has an N-type source region
14
and an N-type channel region
17
, both of which are formed in the P-type gate region
15
. The JFET
2
further has an N-type drain region
16
, formed opposite the source region
14
with the channel region
17
between, as shown in
FIGS. 46 and 47
.
As shown in
FIG. 45
, the N-type drain region
16
of the JFET
2
extends around the entire photoelectric conversion device, and it thus becomes the boundary region between any two adjacent photoelectric conversion devices. The N-type drain region
16
is continuous with the high-density N-type semiconductor layer
13
lying near the top surface of the photodiode
1
and the N-type well region
11
, as shown in
FIGS. 46 through 48
. Accordingly, the N-type regions
11
and
13
, in the PN junction which constitutes the photodiode
1
, are electrically connected to the N-type drain region
16
of the JFET
2
.
The P-type gate region
15
of the JFET
2
sandwiches the N-type channel region
17
from above and below. This structure can reduce the substrate-bias effect, and can increase the gain of the source follower action, while reducing variation in the gain.
The transfer gate
3
consists of a gate electrode positioned above the boundary between the P-type charge-accumulation region
12
and the P-type gate region
15
of the JFET
2
, and separated from the boundary by an insulating film, as shown in FIG.
47
. The transfer gate
3
transfers the charge accumulated in the P-type charge-accumulation region
12
of the photodiode
1
to the P-type gate region
15
of the JFET
2
.
Thus, the P-type charge-accumulation region
12
, the transfer gate
3
, and the P-type gate region
15
of the JFET
2
together constitute a P-channel MOS transistor.
The reset drain
4
has a P-type charge-drain region
18
formed in the N-type well region
11
, as shown in
FIGS. 46 and 48
. The reset drain
4
controls the electric potential of the P-type gate region
15
of the JFET
2
via the reset gate
5
.
The reset gate
5
consists of a gate electrode positioned above the boundary between the P-type gate region
15
of the JFET
2
and the P-type charge-drain region
18
. The gate electrode is separated from the boundary region by an insulating film, as shown in FIG.
46
. The reset gate
5
controls the electrical connection between the P-type gate region
15
of the JFET
2
and the P-type charge-drain region
18
of the reset drain
4
.
The P-type gate region
15
of the JFET
2
, the reset gate
5
, and the P-type charge-drain region
18
of the reset drain
4
together constitute a P-channel MOS transistor.
The conventional photoelectric conversion device also has a transfer-gate interconnection
20
, a reset-gate interconnection
21
, a relay interconnection
23
, a reset-drain interconnection
24
, a vertical signal line
22
, and a drain interconnection
25
, as shown in the figures.
FIGS. 49 through 52
illustrate a portion of a conventional photoelectric conversion apparatus that uses the photoelectric conversion device(s) of
FIGS. 45-48
as pixels arranged in a matrix.
FIG. 49
is a plan view;
FIG. 50
is a cross-sectional view taken along the X
1
-X
2
line shown in
FIG. 49
;
FIG. 51
is a cross-sectional view taken along the Y
1
-Y
2
line shown in
FIG. 49
; and
FIG. 52
is a cross-sectional view taken along the Y
3
-Y
4
line shown in FIG.
49
.
In this conventional photoelectric conversion apparatus, the N-type source regions
14
of the JFETs
2
in each column of the pixel matrix are connected in common to the associated vertical signal line
22
in the vertical scanning direction.
The N-type drain regions
16
of the JFETs
2
of each pixel are continuous around the pixels and from pixel to pixel, extending like a lattice surrounding the pixels, as shown in FIG.
49
. The N-type drain regions
16
of each column are each connected in common, in the vertical scanning direction, to the associated drain interconnection
25
via a contact hole
32
(
FIG. 49
) formed in the interlayer insulating film
33
(FIG.
50
). The drain interconnections
25
are connected in common to another interconnection (not shown) at the top end and at the bottom end of the pixel matrix.
The drain interconnections
25
are formed for the purpose of supporting or reinforcing the diffusion layer of the N-type drain regions
16
with metal interconnections in order to reduce (or shunt) the resistance, and they are required for a photoelectric conversion apparatus having a sufficiently large number of pixels (for example, 500 to 1000 pixels in both the horizontal and vertical directions). If the number of pixels is relatively small, the drain interconnections
25
may be omitted.
As shown in
FIG. 49
, the transfer gates
3
in each row are connected in common, in the horizontal scanning direction, to the associated transfer gate interconnection
20
. The reset gates
5
in each row are similarly connected in common, also in the horizontal scanning direction, to the associated reset gate interconnection
21
.
As shown in
FIGS.

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