Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-01-05
2002-02-05
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S069000, C365S207000
Reexamination Certificate
active
06345010
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor storage device, and more particularly to a cache memory which is to be incorporated in a data processor such as microprocessor or microcomputer.
BACKGROUND OF THE RELATED ART
It is desirable for increasing the operating speed of a cache memory that the writing and reading operations of the cache can be concurrently performed. A construction for executing read/write parallel processing for this purpose by the use of two global bit lines is disclosed in related Japanese Patent Application No. 16223/1997.
SUMMARY OF THE INVENTION
In the related art, the problem of crosstalk arises by operating the two global bit lines in parallel. It is an object of the present invention to realize fast access in a semiconductor storage device while avoiding the problem of crosstalk. According to the present invention, a layout or structure of a semiconductor storage device which is well suited to a cache memory contributes to increasing the operating speed of the device.
A semiconductor storage device according to one aspect of the invention includes a plurality of word lines, a plurality of bit lines, memory cells which are connected to the word lines and the bit lines, a sensing (reading) global bit line which is connected to a sense amplifier, a writing global bit line which is connected to a write amplifier, and a selection circuit which selectively connects at least one of the sensing and writing global bit lines with the bit line.
According to this aspect, the first and second writing global bit lines are arranged between the first and second sensing global bit lines, with the first writing global bit line held adjacent to the first sensing global bit line and with the second writing global bit line held adjacent to the second sensing global bit line; and the distance between the first writing global bit line and the first sensing global bit line, or the distance between the second writing global bit line and the second sensing global bit line is set longer than the distance between the first and second writing global bit lines. With such a construction, the crosstalk between the writing and reading global bit lines, especially the influence of the writing bit lines on the reading bit lines can be relieved.
In a practical device application of the invention, the writing global bit lines and the sensing global bit lines are made of an identical wiring layer, and the distance between the writing global bit lines is greater than the distance between adjacent pairs of the writing and sensing global bit lines. On this occasion, a first wiring layer for making the bit lines, a second wiring layer for making the word lines, and a third wiring layer for making the writing and sensing global bit lines can be formed, as counted from a substrate side.
As another example, the writing global bit lines and the sensing global bit lines are made of different wiring layers, and the horizontal distance between the writing global bit lines and the sensing global bit lines is substantially the same. With this arrangement, the effect of relieving the crosstalk can be attained by using different layers without changing the pitches between the bit lines.
As a practical device, the semiconductor storage device can be so constructed that a first wiring layer for making the bit lines, a second wiring layer for making the word lines, a third wiring layer for making the sensing global bit lines, and a fourth wiring layer for making the writing global bit lines are formed as counted from a substrate side.
Further, it is suitable to provide a part of an arrangement in which the first writing global bit line and the second writing global bit line cross over/under one another. More specifically, the first writing global bit line and the second writing global bit lines cross over or under so that their positions (bit line positions) alternate periodically. Owing to such an arrangement, the crosstalk influence of the writing global bit lines can be relieved.
According to a practical application of the invention, a device is provided having a plurality of word lines, a plurality of bit lines, memory cells which are connected to the word lines and the bit lines, sensing global bit lines which are connected to a sense amplifier, writing global bit lines which are connected to a write amplifier, and a selection circuit which selectively connects at least one of the sensing and writing global bit lines with the bit line; and a part of an arrangement of the global bit lines in which two adjacent ones of the writing global bit lines cross over/under one another.
Here, the two adjacent writing global bit lines may well be arranged between two of the sensing global bit lines. Further, the shortest distance between the writing global bit lines should desirably be longer than the shortest distance between the writing global bit line and the sensing global bit line.
In a practical circuit layout, the plurality of word lines, the plurality of bit lines, and the memory cells connected to the word lines and the bit lines form a first region of a rectangular shape, and a second region of rectangular shape in which the selection circuit is arranged is located along one side of the first region, and that the sensing global bit lines and the writing global bit lines traverse the first and second regions in a direction which is orthogonal to the one side.
Herein, the two writing global bit lines may cross over/under one another in the second region. Besides, a plurality of sets each including the first and second regions may well be arranged in a direction in which the sensing global bit lines and the writing global bit lines extend, so as to define a train of memory banks. Further, a third region which includes the sense amplifier and the write amplifier may well be provided at one end of the memory bank train. It is also contemplated by the invention to arrange two such memory bank trains in parallel and to interpose a decoder/word driver between the two trains.
The layout of a semiconductor storage device proposed by the present invention includes a first region of rectangular shape which is formed by a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines, sensing global bit lines which are connected to a sense amplifier, writing global bit lines which are connected to a write amplifier, and a selection circuit which selectively connects at least one of the sensing and writing global bit lines with the bit line.
Herein, a second region of rectangular shape in which the selection circuit is arranged is located along one side of the first region, and the sensing global bit lines and the writing global bit lines traverse the first and second regions in a direction which is orthogonal to the one side. Further, a plurality of sets each including the first and second regions are arranged in a direction in which the sensing global bit lines and the writing global bit lines extend, so as to define a train of memory banks, and a third region which includes the sense amplifier and the write amplifier is provided at one end of the memory bank train.
In particular, the sense amplifier should desirably be located nearer to the memory bank train than the write amplifier. The reason therefor is that the sense amplifier handles weaker or more feeble signals. It is also contemplated that the sense amplifier includes sense amplifiers of a first stage, a middle stage and a rear stage arranged in such an order as viewed from a side which is nearest to the memory bank train, and that a gate length of each of transistors constituting the first stage is greater than a gate length of each of the transistors constituting the middle stage and the rear stage. From the standpoint of a manufacturing process, dummy transistors which do not operate may well be included among the transistors constituting the first stage.
The transistors constituting the middle stage or the rear stage may, in one arrangement, have their sources, gates and d
Maruyama Hiroshi
Nishioka Naotoshi
Osada Kenichi
Shimazaki Yasuhisa
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Zarabian A.
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