Pre-divider architecture for low power in a digital delay...

Details Pre-divider architecture for low power in a digital delay... Pre-divider architecture for low power in a digital delay...

2001-03-30

2002-12-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S151000

Reexamination Certificate

active

06492852

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories and more particularly, to an improved delay locked loop (DLL) circuit design for power conservation that synchronizes a system clock with data output lines.
2. Description of the Related Art
Semiconductor memories, such as synchronous dynamic random access memories (SDRAMs), rambus DRAM, a synclink DRAM and Double Data Rate (DDR-SDRAM) memories, typically include delay lock loop (DLL) circuits. DLLs function to cancel on-chip amplification, signal processing and buffering delays. DLLs also improve input/output timing margins, the output from which include a latency adjusted read clock signal. A “read” operation in DDR-SDRAMs are designed such that signal transitions present on output data lines (DQs) are synchronized to transitions of the system clock. The DLL circuit requires significant additional current to power the memory device, where lowest power requirements are desirable. When using a DLL circuit to generate this latency adjusted read clock output signal, the DLL typically operates at either the same or twice the system clock depending upon the design, this can lead to a significant power requirement. Recent concerns have brought about many ways of reducing this power demand. Most of these approaches include a trade-off between power and resulting accuracy of the latency adjusted clock. One solution to reduce power requirements is to update the DLL less frequently, which in turn reduces the accuracy of the read clock. This is accomplished by placing a divider in front of the update/control circuitry, thus forcing the control circuitry to operate at a lower frequency and reducing power usage.
There are many types of DLL's formed from analog, digital or a combination of analog and digital circuits that provide control to an adjustable delay line. The “real” on-chip delays for which the DLL is designed to null-out is conventionally “modeled” as a delay block which is placed within the DLL's feedback path. The mimic delay block is constructed in such a manner as to match the total delay of the “real” on chip delays associated with component elements such as, an input receiver, signal processing/data path circuits, output driver, package, on chip RC wire and associated buffering.
FIGS. 1-4
are not necessarily prior art and may not be generally known to those ordinarily skilled in the art at the time of filing of the invention. These figures are provided to illustrate the state in the art and may not be well known. As shown in
FIG. 1
, conventional memory chips using the “modeled” delay (i.e., mimic
40
) often use an inverter chain or similar techniques to account for delays. The accuracy or ability of the mimic block
10
to match the “real” delay is an important parameter since it directly effects the final phase alignment between the transitions edges of the clock signal VCLK (inputs) and the DQ (outputs) signals.
The task of the DLL circuit is to generate an on-chip signal, which is precisely adjusted in time such that, when said signal is used by subsequent on chip circuits (i.e., data path first-in-first-out buffer+OCD) the desired aforementioned edge aligned phase relationship is achieved between VCLK (in) and DQ (out). The DLL generated output signal meeting these requirements will hence forth be refereed to as the “latency adjusted read clock signal.”
A generalized form of a digital DLL is shown in FIG.
1
. External differential signals CLK/CLKb are connected to Input circuit
10
. Input
10
receives and amplifies the crossing of differential signals CLK/CLKb and outputs a reference clock (Ref_clk) signal. The operation of the control circuit
60
is synchronous with the Ref_clk signal. Ref_clk is connected to the input of delay chain
20
and phase detector
50
. Ref_clk is further delayed by a delay circuit (delay chain)
20
and passed to output driver circuit
30
. The resulting signal is split inside of output
30
into two signals. The first of the two signals resulting from the split is buffered and becomes an output of DLL
5
called “latency adjusted read clock,” that can be part of a DRAM memory chip. The second signal from the split becomes an input to the mimic circuit
40
. The output signal of mimic circuit
40
is the feedback clock (Fb_Clk) signal.
Other components include a phase detector circuit
50
for detecting a phase difference between the reference clock signal (ref_clk) and a feedback clock signal (Fb_clk). A delay control circuit
60
receives as an input signal, the output of the phase detector circuit
50
. The delay control circuit
60
includes logic circuitry, which processes instructions from the phase detector. The phase detector
50
indicates whether the Fb_clk signal leads or lags the Ref_clk signal in time. Depending on the design, the phase detector may also indicate the extent to which the lead/lag condition exists. This relationship is communicated to control circuit
60
, which in turn provides instruction to the delay chain
20
to increase or decrease its input-to-output propagation delay in order to compensate for the lead/lag condition present at the phase detector. This inspection and correction process continues until the DLL's closed loop system has properly adjusted the total propagation time of the delay chain
20
in such a manner that Ref_clk and Fb_clk signals are perfectly aligned at the phase detector
50
. Once the DLL converges on a solution, the DLL is said to be “locked,” and at other times, it remains “unlocked”. Assuming that mimic circuit
40
accurately reflects the delay for which the DLL is to remove, such a system will produce a latency adjusted read clock that can be used to control other on-chip data processing circuit and ultimately produce DQ signal outputs which are synchronized/aligned with the external CLK signals.
DLL circuits have also been implemented using a divider circuit
70
to reduce power and update DLL states less frequently, as shown in FIG.
2
. One problem with this design is that only the delay line's control circuit
60
is operated at a reduced rate/power, leaving the phase detector
50
mimic circuit
40
, and delay chain
20
operating at the original higher rate/power levels. Another problem with this architecture is that the maximum operational frequency for which the DLL can sustain is limited. When the reference clock is used to change the operating state pointer of the delay chain circuit and the same reference clock signal propagates through the delay chain circuit, the pointer must update before the reference clock changes states. In other words, as the frequency is increased, the changing of the pointer for the delay chain effects the reference clock being propagated through the delay chain (line). The term “pointer” herein is defined as a digital (or analog) informational state from the control circuit
60
which produces a unique amount of propagation delay within the delay chain/line
20
. That is, the control
60
is “pointing” to a location/state for which the delay line is complying and producing a unique amount of propagation delay.
Another form of DLL architecture is shown in
FIG. 3
that uses the output of the delay chain (line)
20
as the clock signal for the control circuit
60
. This architecture enables a higher frequency of operation since the length of the delay chain (line)
20
is of no consequence. Yet another DLL design (
FIG. 4
) uses this higher frequency DLL architecture and includes an additional divider circuit (post-divider
90
) in the feedback path. The introduction of the post-divider circuit
90
reduces the power consumption in the control circuit
60
, mimic
50
and phase detector
40
. However, since the maximum frequency is determined by the propagation delay from the output of the delay chain (line) to when the pointers change, any increase in propagation delay such as adding a post-divider
90
will decrease the maximum frequency of operation that the DLL can sustain. To eliminate this unwan

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