Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-08-21
2002-10-08
Feild, Lynn D. (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S704000, C361S753000, C361S799000, C361S816000, C174S051000, C174S034000
Reexamination Certificate
active
06462943
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the arrangement of components in a computer system and, more particularly, relates to the mounting of a Very Large Scale Integration (VLSI) chip on the chassis of a personal computer.
BACKGROUND OF THE INVENTION
A Very Large Scale Integration (VLSI) chip is generally composed of a silicon die having an integrated circuit fabricated thereon, a package for housing the silicon die that can be made of ceramic, organic or other types of chip carrier packages, and various means of electronic connection to the silicon die that extends to the exterior of the package for connection in an electronic system. Transistors and other circuit components reside on the silicon die in printed form and require power and signal connection extending to the exterior of the package. These connections would typically be coupled to a printed circuit board for further integration with other electronic components. The component features of the silicon die are extremely small, in the order of 0.1 to 1 micro-meter (Micron), whereas the features in the printed circuit board are in the order of 0.1 to 1 millimeter (mm). The connection configurations of a chip package bridge this large scaling gap by providing power and signal connections between the silicon die and the printed circuit board.
Referring to
FIG. 1A
, one configuration of a conventional chip package
100
is shown. The VLSI chip
102
is shown mounted on a ceramic base
104
and is connected via bond wires
106
to connection pins
108
through pin circuitry
112
of the chip package
100
. The ceramic base
104
is coupled to the chip package
100
to dissipate heat from the VLSI chip
102
into the ambient outside the chip package
100
. Also, the bond wires
106
are often a tenuous connection in the package
100
and are subject to defects. The connection pins
108
are configured to mount on a circuit board for further connection to other components.
Referring now to
FIG. 1B
, a top view of the chip package
100
is shown where bond wires
106
connect bonding pads
110
to the pin circuitry
112
. As a result of manufacturing constraints, a design utilizing bond wires
106
such as in the chip package
100
have a limited access to pads
110
such that the pads
110
reside only on the periphery of the VLSI chip
102
. Thus, the number of power and signal connections are greatly limited by the number of pads that can be accessed around the periphery of VLSI chip
102
.
A second configuration of a conventional chip package
114
is shown in FIG.
1
C. This configuration is known in the art as a “C-4 mount.” In this configuration, the VLSI chip
116
is connected to the pin circuitry
118
via soldering bumps
120
located on the bottom surface of the VLSI chip
116
. Here, the chip is inverted, or flipped, so that connections can be made to pins
108
. As can be seen in
FIG. 1D
, this configuration allows a greater number of landing pads
122
on the surface of the VLSI chip
116
since the design is not limited to placing the landing pads on the periphery of the surface of VLSI
116
. This solves the need for the increasing number of connections required to VLSI chips, particularly, microprocessors that have ever increasing demands for more signal connections and more power. An increase in the number of connections to the landing pads
122
allows for more signal lines and power lines to the VLSI chip. Also, the bond wires used in the design of
FIG. 1
are eliminated. Details regarding one method of solder connections used in joining integrated semiconductor devices are found in related application “Multilayer Solder Interconnection Structure” of Mashimoto et al. cited above. Demands for higher power and more signals, however, continue to increase.
With each new generation VLSI chips continue to grow in complexity, performance and power consumption. As a result, the current demands for the chips have also increase. One of the biggest challenges for future generations of chips is managing the chip's power consumption. Presently, the power consumption of a typical microprocessor is between 1 and 60 watts. As new generations of microprocessors are developed, however, the power demands are expected to increase into the hundreds or even thousands of watts as complexity of the chip increases and as better chip performance is demanded. Also, as more complicated microprocessors are developed, more transistors are used, the size of the silicon die grows and the signal frequency greatly increases. The net effect is that the power and current demands will continue to be major concerns in chip design.
One modem solution to manage increased power demand is voltage scaling. Voltage scaling is the process of reducing the voltage level of signals located inside and outside the VLSI chips so that less power is demanded. Power has a quadratic relationship to voltage where power is proportional to the square of the voltage. Hence, if the supply voltage is reduced by half, the power is reduced by one-fourth, giving a dramatic decrease in the power demand. Voltage scaling continues to be practiced in modem chip designs. For example, in the 1980's, the typical power supply voltage was 5 volts. Later in the 1990's, the average supply voltage was reduced to 3.3 volts. More modem designs have reduced the supply voltage to as low as 2.5 volts and even 1.8 volts. Voltage scaling, however, has its limits and the continuing increase in power and current demands are still inevitable.
CURRENT DEMAND
Unlike power, current is linearly proportional to voltage. Therefore, if the supply voltage is reduced by half, the current is also reduced by half. Hence, voltage scaling only reduces supply currents by the same rate as reduction in voltage. Referring to
FIG. 2
, a logarithmic graph shows how microprocessor current demands have changed over the years. For example, the Intel 386 microprocessor had a current demand of less than 0.2 amperes. In 1989, the Intel 486 microprocessor had twice the demand of the 386 microprocessor of approximately 0.4 amperes. Still further, the Pentium processor, available in 1993, had a much higher power demand of around 3 amperes. At this rate, according to the projected graph of
FIG. 2
, as time goes on, the current demand for microprocessors will greatly increase into the hundreds and even thousands of amperes.
As mentioned above, the present designs of chip packages supply power and ground currents to the silicon die using package pins, bond wires, solder bumps and landing pads on the die. As current and signal demands increase, the number of package pins and VLSI landing pads will increase dramatically in order to meet the demand of the current supplies and signal connections. Conventional technology can allow for around 100 milli-amperes for each landing pad on the die without sacrificing performance of the chip. As a result, as complexity, performance and power demands increase, a larger number of landing pads and pins will be required that consume a great amount of space on the silicon die. All of these factors increase the cost of producing the chip.
In conventional systems, supply current and ground current sources are connected to the chip packages in the same fashion as communication signals. The supply current and ground current connections supply the energy needed for the VLSI chip's operation. Unlike the signal connection, the supply current and ground current sources (Vcc, Vss, respectively ) have very few connections to the chip. The communication lines, however, carry a very low amount of current and are greater in number. As power demand increases, however, a larger number of supply and ground current connections will be needed in order to keep up with the higher demanding VLSI chips. A major problem is that for every supply and signal there exists one pin on the package, one bond wire or solder connection to the die and one landing pad on the die. As complexity increases, the chip package becomes crowded with electrical connections. One
Borkar Shekhar Yeshwant
Dreyer Robert S.
Mulder Hans J.
Feild Lynn D.
Intel Corporation
Lam Peter
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