Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-01-05
2002-08-06
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S694000, C438S697000, C438S723000, C438S724000
Reexamination Certificate
active
06429135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a spacer, and more particularly, to a method of forming a silicon nitride spacer for reducing the stress between the silicon nitride spacer and a substrate.
2. Description of the Prior Art
In semiconductor devices, a metal oxide semiconductor (MOS) transistor is composed of a gate, a drain, and a source. Both the structure and the quality of the gate in the MOS transistor decide the electrical performance of the MOS transistor. In present semiconductor processes, two spacers of dielectric material are typically formed on either side of the gate in order to protect the gate from damage and ensure the electrical performance of the gate. In addition, the spacers can be used as a hard mask in the subsequent ion implantation process for the formation of the source and drain of the MOS transistor.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are schematic diagrams of a prior art method of forming a spacer
28
around a gate
22
. The spacer
28
around the gate
22
is positioned on a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
includes a substrate
12
, and a dielectric layer
14
positioned on the substrate
12
functioning as a gate oxide. Each gate
22
includes a conductive layer
16
positioned on the dielectric layer
14
, and a silicide layer
18
positioned on the conductive layer
16
to reduce the resistance of the conductive layer
16
. A cap layer
20
is positioned on top of the gate
22
to protect the gate
22
. The dielectric layer
14
is formed of silicon dioxide, and the conductive layer
16
is formed of doped polysilicon. Tungsten silicide is a typical material used in the formation of the silicide layer
18
, and silicon nitride is commonly used to form the cap layer
20
.
As shown in
FIG. 2
, an ion implantation process is performed to form doped regions
30
adjacent to the gates
22
in the silicon substrate
12
. The doped regions
30
are used as lightly doped drains of the MOS transistor. A low-pressure chemical vapor deposition (LPCVD) is then performed to form a silicon nitride layer
26
to uniformly cover both the gate
22
and the silicon substrate
12
.
As shown in
FIG. 3
, an anisotropic dry etching process is performed to remove portions of the silicon nitride layer
26
positioned on both the gate
22
and the silicon substrate
12
. Portions of the silicon nitride layer
26
remaining around the walls of the gate
22
thereby form the spacers
28
. As shown in
FIG. 4
, using the spacers
28
as hard masks, another ion implantation process is performed to form doped regions
32
beneath each of the doped regions
30
in the substrate
12
. The fabrication of the MOS transistor is thus complete, whereby the doped regions
32
are used as the source and the drain of the MOS transistor.
Silicon nitride, a material having a high dielectric constant, is used to form the spacers
28
in the prior art method. However, the tension stress of silicon nitride is greater than 10
10
dyne/cm
2
so that high stress occurs between the spacer
28
and the substrate
12
, and between the spacer
28
and the gate
22
. The resulting high stress may cause the spacer
28
to strip away from the substrate
12
due to poor adhesion between the spacer
28
and the substrate
12
. Consequently, less protection and a greater amount of leakage occur in the gate
22
to affect product reliability.
In addition, in the prior art method of forming a word line structure in the dynamic random access memory (DRAM) process, silicon nitride is used to form the cap layer
20
, located on top of the gate
22
, and the spacers
28
, that is, the gate
22
is surrounded by silicon nitride. Since the dielectric constant of silicon nitride materials is greater than that of silicon oxide materials, a larger couple capacitance occurs between the word line and a bit line, and between the word line and a storage node.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the pre sent invention to provide a method of reducing stress between the silicon nitride spacer and the substrate on a semiconductor wafer so as to solve the problems of the prior art.
In a preferred embodiment of the present invention, the semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. A dielectric layer is first formed on the semiconductor wafer covering the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer to reduce the stress between the silicon nitride spacer and the substrate.
It is an advantage that the present invention uses silicon oxide to replace portions of the silicon nitride spacer around the gate, so that stress is reduced between the silicon nitride spacer and the silicon substrate, to further reduce leakage in the MOS transistor. As well, the couple capacitance between the word line and the bit line, and between the word line and the storage node is also reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5789304 (1998-08-01), Fisher et al.
patent: 6060351 (2000-05-01), Parekh et al.
patent: 6090677 (2000-07-01), Burke et al.
patent: 6207485 (2001-03-01), Gardner et al.
Chern Horng-Nan
Lin Kun-Chi
Hsu Winston
Tran Binh X
United Microelectronics Corp.
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