Transaction checking for system architecture validation

Details Transaction checking for system architecture validation Transaction checking for system architecture validation

1998-07-06

2002-12-17

Choi, Kyle J. (Department: 3623)

Data processing: structural design, modeling, simulation, and em

Emulation

Compatibility emulation

C703S017000, C714S037000, C714S045000

Reexamination Certificate

active

06496792

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to testing computer systems, and more specifically, to system architecture validation.
BACKGROUND
Thorough pre-silicon testing of integrated circuits and computer systems is an essential step in obtaining a production quality design. However, there are hindrances to the successful validation of increasingly-complex designs: difficulty in discovering subtle errors in simulation results, the lack of consistent and comprehensive checking methodologies for complex transaction scenarios, and the extensive time and experience required for quality simulation analysis.
To effectively validate a system, simulation results must be analyzed. The results should be analyzed in real time or captured for post-simulation analysis. During the simulation, all system activity is recorded in log files called trackers. These trackers, located at each transaction interface, provide a macroscopic view of bus transactions. The host tracker, for example, lists all processor bus activity as well as second-level cache cycles, inquire/snoop cycles, and system interrupts. Generally, trackers are located at all system transaction and event interfaces, including main memory (DRAM), industry standard architecture (ISA) bus, and peripheral component interconnect (PCI) bus. Once simulation events have been recorded for a particular test suite, they must be evaluated for correctness.
One prior art method of evaluation is to obtain an initial “good” simulation. This is done by actually visually inspecting the output of an initial simulation and determining its accuracy. For each type of test, an initial good simulation must be performed and inspected.
Further simulations are compared against the results of the known good simulation. There are several weaknesses with this approach. First, although one assumes that the prior “good” simulation is free of bugs, it may still contain errors that were missed by the visual inspection. Second, methods for comparing the results of the initial good simulation and the current simulation must be sophisticated (as opposed to the simple UNIX “diff” program) to provide for allowable differences, such as system latency, but detect subtle differences like single bit errors. A subtle error may pass undetected during an early test and propagate through subsequent testing because its “diff” is clean.
An example of comparing an initial good simulation with simulation runs was performed. Bus trackers were generated and stored for each of the suite of seven-hundred and fifty regression tests. A variant of the UNIX “diff” program was created to compare the results of each test to prior “known good” results. This tedious, error prone process required one week for an engineer to review all the observed differences. On several occasions, the “known good” results were found to have errors, and differences that showed bugs were ignored.
Thus, a tool that consistently analyzes simulation results in an automated fashion independent of the results of previous simulation iterations would be advantageous.
SUMMARY OF THE INVENTION
A method and apparatus for transaction checking for system architecture validation are described. Tracking data is received from trackers in the system. The tracking data is parsed to construct queues. These queues are compared with each other. For one embodiment, the queues are further compared with predicted behavior of the element that was tested. Discrepancies between the queues and the predicted behavior are flagged.


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Tayal, S. et al. “System Level Verification of ASIC Chipsets,” 6th Annual IEEE Int'l ASIC Conf. and Exhibit. Sep. 27-Oct. 1, 1993.

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