Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-06-11
2002-04-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S119000
Reexamination Certificate
active
06372550
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a high-output-power field-effect transistor (FET) connected to a package by a face-down system.
RELATED ART
The semiconductor device, formed of a GaAs based semiconductor material, is used in a majority of cases as a semiconductor device for which high-speed response is required in view of its characteristics as a material. However, since heat evolution in an element deteriorates characteristics of the semiconductor device, there is presented a problem of how to improve the cooling efficiency of the device.
For example, in a semiconductor device of the type of dissipating the heat evolved from the semi conductor substrate, there is used a technique of reducing the thickness of the GaAs substrate having low thermal conductivity to assist in thermal diffusion (heat dissipation). However, the semiconductor device suffers from a drawback that, if the substrate is reduced in thickness, the device is lowered in mechanical strength. For increasing the thermal diffusion (heat dissipation) efficiency without weakening the mechanical strength, there is disclosed in, for example, the JP Patent Kokai JP-A-59-124750 and JP Patent Kokai JP-06-005633, a method for interconnecting a substrate and a heat sink via an electrically conductive layer.
On the other hand, in a semiconductor device of the type in which the heat evolved from the device is dissipated from an electrode on the semiconductor substrate surface provided with the insulating film or the electrode, there is used a technique of dissipating the heat via an electrically conductive member electrically connected to the electrode or a heat sink member.
In particular, in the high-output-power field effect transistor (FET), there is routinely used flip-chip mounting of the face-down system in which a gate electrode interconnection formed on a GaAs substrate is intimately contacted with the package heat sink.
FIG. 12
shows the cross-section of a conventional semiconductor device, while
FIG. 13
shows the cross-section of the semiconductor device of
FIG. 12
mounted on a package.
Referring to
FIGS. 12 and 13
, the manufacturing method of a conventional semiconductor device is explained step-by-step.
Referring to
FIG. 12
, a gate electrode
2
is first formed on a substrate of, for example, GaAs, and subsequently a first insulating film
7
is deposited on the entire surface of the substrate
1
. At areas of the first insulating film
7
in which a source electrode
4
and a drain electrode
3
are formed, holes are formed, and TiAu sputtering is then applied to form an electrically conductive layer for plating followed by Au plating to form the source electrode
4
and the drain electrode
3
.
A second insulating film
8
is then deposited on the entire surface to overlie the first insulating film
7
, source electrode
4
and the drain electrode
3
and planarized. The area of the planarized second insulating film
8
in register with the source electrode
4
is then bored, i.e. the exposed portion (bore in a mask) of the second insulating film
8
is removed. Then, TiAu etc. designed to serve as an electrically conductive layer for the plating is sputtered on the entire surface to form a thick plating film of Au resulting in an electrically conductive member
6
. This gives an active element having a cross-sectional shape as shown in FIG.
12
.
The active element, shown in
FIG. 12
, is bonded by thermal pressure bonding to a package heat sink
9
by the face-down system to effect flip-chip mounting, as shown in FIG.
13
.
SUMMARY OF THE DISCLOSURE
However, in the course of the investigations toward the present invention the following problems have been encountered. Namely, the above-described conventional semiconductor device has the following drawbacks. Referring to
FIG. 14
, schematically illustrating the drawbacks of the conventional semiconductor device shown in
FIG. 13
, the thermal diffusion (heat dissipation) path
13
is solely a path connecting from the source electrode
4
via the electrically conductive member
6
to the package heat sink
9
, while there is no heat conducting path for the heat evolved on the side of the drain electrode
3
, so that the heat evolved on the semiconductor device cannot be dissipated efficiently towards the package.
In view of the above drawbacks, it is an object of the present invention to provide a semiconductor device which is capable of dissipating the heat evolved on the semiconductor device efficiently towards the package, and a manufacturing method therefor.
For accomplishing the above object, the present invention provides a device in which an insulator having high electrical insulating properties and high thermal conductivity above (on top of) a drain electrode and in which this insulator is thermally contacted with a lead-out interconnection layer of a source electrode.
According to the present invention, generally, there is provided a semiconductor device comprising:
a plurality of heat dissipating paths, each for each of a pre-set number of terminals of an active element, the heat dissipating paths being adapted for transmitting heat from the terminals of the active element to a heat sink member, wherein
the pre-set number of terminals being constructed so as not being electrically connected to one another by the heat radiating paths and the heat sink members.
In the semiconductor device, in at least one of the heat dissipating paths, there is inserted in a path reaching the heat sink member a member exhibiting good thermal conductivity and electrically insulating properties, termed as an “insulating member”.
Also there is provided a semiconductor device wherein a first terminal of the active element is connected via an electrically conductive member to a heat sink member, and wherein a second terminal of the active element transmits heat to the heat sink member via at least an insulating member interposed in-between.
In one aspect, the present invention provides an arrangement in which an electrically conductive member connected to a terminal of an active element formed on a substrate is connected via an insulating member to the other terminal of said active element and in which said electrically conductive member is connected to a heat sink member of the package accommodating said active element.
In another aspect, the present invention provides an arrangement in which a terminal of an active element formed on a substrate is connected via an insulating member to a heat sink member of a package used for mounting said active element.
The present invention provides a method for producing a semiconductor device in which an active element formed on a substrate is connected to a heat sink member of a package accommodating the active element, comprising the steps of:
(a) forming a gate electrode on the substrate;
(b) forming a first insulating film having holes provided in the substrate at positions of a drain electrode and a source electrode respectively;
(c) forming the drain electrode and the source electrode on the substrate;
(d) forming a second insulating film on the entire surface of the substrate and planarizing the surface until the drain electrode and the source electrode are exposed;
(e) forming an insulating member on the drain electrode;
(f) forming on the substrate a third insulating film having a hole provided in register with the source electrode and planarizing the surface until the surface of the insulating member of the drain electrode is exposed; and
(g) forming an electrically conductive member on the third insulating film.
Preferably, all or part of the insulating member may be a member comprising aluminum nitride, while a high-output-power FET formed on a GaAs substrate may be used as an active element.
Other features of the present invention will become apparent from the entire disclosure including claims and accompanying drawings.
REFERENCES:
patent: 5757081 (1998-05-01), Chang et al.
patent: 49-11580 (1974-02-01), None
patent: 55-151371 (1980-11-01), Non
Asano Kazunori
Kohno Junko
Fourson George
NEC Corporation
Pham Thanh V
Scully Scott Murphy & Presser
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