Active solid-state devices (e.g. – transistors – solid-state diode – With specified shape of pn junction
Reexamination Certificate
2000-07-25
2002-12-03
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With specified shape of pn junction
C257S490000, C257S495000, C257S496000, C257S599000, C257S600000
Reexamination Certificate
active
06489666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a technique for reducing heat generation of a semiconductor device to stabilize the operation thereof.
2. Description of the Background Art
FIG. 6
is a vertical cross-sectional view for illustrating a background art semiconductor device
101
P. As shown in
FIG. 6
, the semiconductor device
101
P comprises an N
−
type semiconductor substrate
1
P made of silicon or the like, and a P layer
2
P is formed in a surface S
1
P of the semiconductor substrate
1
P. The P layer
2
P is formed in contact with a beveled surface S
2
P (referred to also as a “surface S
2
P”hereinafter) contiguous with the surface S
1
P. An anode electrode
31
P is formed on the surface S
1
P. An N
+
layer
25
P is formed in a surface S
3
P opposed to the surfaces S
1
P and S
2
P. A cathode electrode
33
P is formed on the surface S
3
P in opposed relation to the anode electrode
31
P.
In general, carrier recombination centers are formed by proton irradiation or the like near a PN junction of the P layer
2
P and the semiconductor substrate
1
P, and control a carrier lifetime near the PN junction. The carrier lifetime in the entire semiconductor substrate
1
P is controlled to be short by heavy metal diffusion, electron beam irradiation or the like.
FIG. 7
is a vertical cross-sectional view for illustrating current flows in the semiconductor device
101
P. In
FIG. 7
, forward current is schematically shown by solid arrows and reverse current is schematically shown by dashed arrows.
FIG. 8
schematically illustrates a reverse recovery operation in the semiconductor device. In general, when switching of an external circuit causes the semiconductor device
101
P to make an instantaneous transition from a forward current flowing state to a reverse-biased state, a large transient reverse current flows because of a minority carrier accumulation phenomenon. Such a reverse current has a current decrease rate determined by the value of the reverse bias and the inductance of the external circuit, and flows for a predetermined length of time.
More specifically, the reverse current flows until excess carriers remaining near the PN junction decrease in number to have a constant concentration or less and a depletion layer is established. When the established depletion layer starts bearing a reverse voltage, the reverse voltage gradually increases in accordance with the expansion of the depletion layer whereas the reverse current gradually decreases. Then, the device voltage becomes steadily equal to the applied reverse voltage, and the reverse recovery operation is completed.
In the background art semiconductor device
101
P, the lifetime near the PN junction is controlled to be short as described above, thereby to decrease a forward voltage and the reverse current and to improve a maximum allowable on-state current rise rate (di/dt).
However, the background art semiconductor device
101
P is disadvantageous in that the higher, for example, a driving frequency and the reverse bias voltage are, the greater a power loss, i.e. heat generation (self heat generation), is. Thus, the operation of the semiconductor device
101
P might encounter a trouble due to the heat generation. At this time, the semiconductor substrate
1
P generates a greater amount of heat in a peripheral portion
1
AP thereof than near a central portion thereof, particularly a portion between the anode electrode
31
P and the cathode electrode
33
P. A cause of such a difference in the amount of heat generation is a poorer heat dissipating ability or heat emitting property of the peripheral portion
1
AP of the semiconductor substrate
1
P than that of the central portion thereof because of the absence of a metal layer such as the anode electrode
31
P and the like on the surface of the peripheral portion
1
AP of the semiconductor substrate
1
P.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises: a first semiconductor layer of a first conductivity type having a first surface, a second surface surrounding the first surface and coupled to the first surface at an angle other than a right angle, and a third surface opposed to the first and second surfaces; a second semiconductor layer of a second conductivity type formed in the first surface; and a third semiconductor layer of the second conductivity type surrounding the second semiconductor layer in non-contacting relationship with the second semiconductor layer, the third semiconductor layer being formed in the first semiconductor layer and in contact with the second surface.
Preferably, according to a second aspect of the present invention, in the semiconductor device of the first aspect, a distance between the second semiconductor layer and the third semiconductor layer in their closely spaced positions is not greater than 50 &mgr;m.
Preferably, according to a third aspect of the present invention, in the semiconductor device of the first or second aspect, the third semiconductor layer extends closer to the third surface than does the second semiconductor layer.
Preferably, according to a fourth aspect of the present invention, the semiconductor device of any one of the first to third aspects further comprises a metal layer formed on the side of the third surface to cover a region of the third surface which is opposed to the second semiconductor layer.
Preferably, according to a fifth aspect of the present invention, the semiconductor device of any one of the first to fourth aspects further comprises a fourth semiconductor layer of the first conductivity type formed in part of the third surface which is substantially opposed to the second semiconductor layer, wherein the fourth semiconductor layer has an impurity concentration higher than the impurity concentration of its surrounding layer.
Preferably, according to a sixth aspect of the present invention, the semiconductor device of any one of the first to fifth aspects further comprises a fifth semiconductor layer of the first conductivity type formed in contact with the third surface, the fifth semiconductor layer having an impurity concentration higher than the impurity concentration of the first semiconductor layer.
In accordance with the first aspect of the present invention, the third semiconductor layer surrounds the second semiconductor layer in non-contacting relationship with the second semiconductor layer, and is formed in the first semiconductor layer and in contact with the second surface. This allows current to converge on the second semiconductor layer and, therefore, on the center of the first semiconductor layer, thereby suppressing heat generation in a peripheral portion of the first semiconductor layer. Therefore, the semiconductor device having the second surface corresponding to a so-called beveled surface can suppress a trouble resulting from the heat generation to perform a stable operation. Additionally, the second surface ensures a breakdown voltage or maximum allowable voltage.
In accordance with the second aspect of the present invention, the distance between the second semiconductor layer and the third semiconductor layer in their closely spaced positions is not greater than 50 &mgr;m. This ensures the suppression of a leakage current flowing when a reverse voltage is applied between the second semiconductor layer and the third surface.
In accordance with the third aspect of the present invention, the third semiconductor layer extends closer to the third surface than does the second semiconductor layer. This effectively alleviates a surface electric field strength at the second surface. Therefore, the increase in breakdown voltage of the semiconductor device is accomplished.
In accordance with the fourth aspect of the present invention, the metal layer is formed on the side of the third surface to cover the region of the third surface which is opposed to the second semiconductor layer. In other words, the metal
Hirano Noritoshi
Satoh Katsumi
Yamaguchi Yoshihiro
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