Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-09-19
2002-12-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S797000, C438S622000, C438S401000
Reexamination Certificate
active
06492734
ABSTRACT:
This application is based on Japanese Patent Application 2001-115501, filed on Apr. 13, all the content of which is incorporated in this application by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device including damascene wiring and a manufacturing method thereof.
2. Description of the Related Art
As the integration degree increases in the manufacturing of semiconductor devices, the respective values stipulated by the design rule become smaller. A technical limit is approaching in a semiconductor fabricating method in which a surface metallic wiring layer of aluminum, wolfram, or the like is formed on a surface of an insulating layer, a resist pattern is formed on the surface metallic wiring layer, and then the surface metallic wiring layer is directly etched.
Semiconductor manufacturers have started adopting a damascene process in place of the method in which the surface wiring layer is patterned by etching. In the damascene process, an inter-layer insulating layer is beforehand formed, wiring grooves and via holes are disposed in the inter-layer insulating layer by etching, and a wiring material is filled in the wiring grooves and the via holes. The damascene process is a suitable method to form narrow wiring in a silicon oxide layer or film.
As a material for the wiring or the wiring layer, aluminum has been mainly used in the prior art. However, aluminum has a technical limit for the following reasons. Aluminum has high resistance, and electro-migration easily occurs in a layer made of aluminum. Therefore, copper is increasingly used because copper has relatively lower resistance and electro-migration occurs less frequently in a layer of copper. Although patterning of copper by etching is attended with difficulty, copper wiring can be formed by the damascene process.
The copper wiring is harder than the aluminum wiring and highly corrosive. For example, when the aluminum wiring is left standing in an atmospheric environment, aluminum oxide Al
2
O
3
is formed on a surface of the aluminum wiring and hence automatically stops the corrosion thereof. On the other hand, when the copper wiring is left standing in an atmospheric environment, oxide of copper CuOx is formed on a surface of the copper wiring. However, the copper oxide film cannot fully stop the corrosion thereof, namely, the copper wiring is corrosive.
Additionally, the copper wiring is hard. This makes it difficult to achieve the bonding process of the prior art. Consequently, there are employed, for example, a bump forming process and a process to form an aluminum pad for wire bonding. These processes increase the number of processing steps. Therefore, the production cost is soared, the defect density is increased, and yield is lowered in the semiconductor manufacturing.
Although the damascene process has already been used as a wiring process, this process is attended with an inherent problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device including novel multilayer wiring structure which can be suitably formed by the damascene process.
Another object of the present invention is to provide a method of manufacturing a semiconductor device including novel multilayer wiring structure which can be suitably formed by the damascene process.
According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate including a plurality of semiconductor elements, a second insulating layer formed on said semiconductor substrate, a damascene wiring depression formed in a surface of said second insulating layer beginning at the surface, said depression having a first width; an aligning groove formed in said surface of said second insulating layer beginning at the surface, said aligning groove having a second width larger than said first width; a damascene wiring formed by filling a substance in said damascene wiring depression, an aligning wiring pattern formed in a wiring layer of said damascene wiring in said aligning groove, said aligning wiring pattern forming a first step; a surface wiring pattern formed on a surface of said second insulating layer, said surface wiring pattern being connected to said damascene wiring; and a first aligning surface wiring pattern formed of a wiring layer which also forms said surface wiring pattern on said aligning wiring pattern, said first aligning surface wiring pattern having a second step reflecting said first step.
According to one aspect of the present invention, there is provided a semiconductor device manufacturing method, comprising the steps of (a) forming a second insulating layer above an underlay including a semiconductor substrate including a plurality of semiconductor elements, (b) forming a wiring groove having a first width in a surface of said second insulating layer beginning at said surface and an aligning groove having a second width larger than said first width, (c) forming second damascene wiring embedded in said wiring groove, said second damascene wiring having substantially a flat surface and forming a wiring pattern in said aligning groove, said wiring pattern having a first step; (d) forming a surface wiring layer on said second insulating layer, said surface wiring layer forming a second step reflecting the first step on said aligning groove; (e) forming a resist layer on said surface wiring layer, exposing and developing said resist layer using the second step as an aligning marker, and resultantly forming a resist pattern; and (f) etching said surface wiring layer using said resist pattern as an etching mask and resultantly forming a surface wiring pattern connected to said wiring pattern.
The process to form a surface wiring pattern on the damascene wiring can be conducted using only one mask.
According to the present invention described above, it is possible to fabricate a semiconductor device including multilayer damascene wiring and surface wiring through a relatively small number of process steps.
On the damascene wiring, a bonding pad, a fuse, or the like can be formed using an aluminum layer. The wiring pattern can also be formed at the same time.
REFERENCES:
patent: 6333519 (2001-12-01), Nakazawa
patent: 6340632 (2002-01-01), Fukada et al.
patent: 5-267336 (1993-10-01), None
patent: 11-330381 (1999-11-01), None
patent: 2000-306822 (2000-11-01), None
Fujitsu Limited
Loke Steven
Owens Douglas W.
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