Flat display unit

Computer graphics processing and selective visual display system – Display driving control circuitry

Reexamination Certificate

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Details

C345S096000, C345S208000, C345S098000, C345S559000

Reexamination Certificate

active

06437775

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
Relates generally to a flat display unit.
2. Description of the Prior Art
Conventionally, amorphous silicon thin film transistors (TFTs) have been used for the display part of an active matrix liquid crystal display unit. However, in recent years, polysilicon TFTs have been often used.
The polysilicon TFT has a higher mobility than that of the amorphous silicon TFT. For that reason, the driving part of the liquid crystal display unit comprises polysilicon TFTs. Therefore, when the display part comprises polysilicon TFTs, a part of the driving circuit (the peripheral driving circuit) of the liquid crystal display unit can be formed on the same substrate as that of the display part.
By the way, the display part of a liquid crystal display unit using polysilicon TFTs substantially has the same construction as that of the display part of a liquid crystal display unit using amorphous silicon TFTs. That is, although data are written on pixel by pixel driving TFTs, the holding characteristic based on only the electrostatic capacitance of the liquid crystal layer is insufficient, so that an auxiliary capacitor is typically connected.
This auxiliary capacitor is arranged for each of the pixels. One electrode of the auxiliary capacitor is connected to a corresponding one of the TFTs, and a potential for forming each capacitor is applied to the other electrode of the auxiliary capacitor. Lines for supplying this potential are arranged in the display part so as to extend typically in parallel to the gate signal lines of the pixel driving TFTS. The line for supplying the potential to the auxiliary capacitor will be hereinafter referred to as an auxiliary capacitance line.
As described above, in the liquid crystal display unit using the polysilicon TFTs, a part of the driving circuit (the peripheral driving circuit) may be formed on a glass substrate. As such a peripheral driving circuit, there is considered a construction wherein analog switches
10
a
,
10
b
combined with a shift register (not shown) are formed on a glass substrate as shown in FIG.
4
.
In this case, as a external driving circuit, an exterior printed-circuit board may be provided with a digital-analog converting part and an output buffer for transmitting data to pixels/signal lines.
In this case, a method for simultaneously transmitting data to some signal lines may be adopted in order to decrease the number of data signal lines. That is, there may be adopted a method for diving pixels to be driven during one horizontal period and for driving each block of some pixels. Moreover, if a block sequential driving method for sequentially driving blocks is adopted, it is possible to further decrease the number of the data signal lines.
For example, a method for driving a screen having an array of 1024 dots in a horizontal direction will be described. That is, the case of XGA of 1024×768 will be described. Furthermore, one dot comprises three pixels of R, G and B.
Assuming that one block has 24 pixels (i.e., 8 dots) connected to 24 signal lines, if each block is sequentially driven during {fraction (1/32)} of one horizontal period, 256 dots can be driven during one horizontal period. This corresponds to ¼ of the screen, so that data signals may be inputted to the screen in four-parallel.
This block sequential driving system has the merits of being capable of decreasing the number of the data signal lines and decreasing the frequency for data transfer. However, this system has the following problems.
That is, when data are written on a certain signal line
24
as shown in
FIG. 4
, the fluctuation in potential of the signal line
24
is transmitted to another signal line
24
via a parasitic capacitor
40
which is produced in a portion wherein the signal line
24
crosses the above described auxiliary capacitance line
30
, so that the fluctuation appears on the screen as noise.
In order to explain this phenomenon, adjacent pixels on a certain auxiliary capacitance line are considered in the case of the block sequential driving system for transferring data every last block.
The fluctuations of the potentials of the auxiliary capacitance lines in one block due to an optional data signal do not often have regularity, so that the fluctuations are canceled out to have a small influence on other signal lines.
However, in a case where data on white and black are alternately repeated every one block, the data lines are simultaneously distorted in the same direction, so that the fluctuations of the potentials of the auxiliary capacitance lines are great (see FIG.
5
). Since the potentials of the auxiliary capacitance lines are typically supplied from a power supply provided outside, the ability to suppress the fluctuations in the screen is low, so that the last fluctuation is not canceled during a write time for one block. For that reason, when data are written on the next block, the potential of the auxiliary capacitance line is different from that when data are written on the last block. Therefore, the potential applied to the liquid crystal varies, so that an image shifted from a predetermined gradation is recognized to cause noise. When the potential of the auxiliary capacitance line further fluctuates due to signals in the written block, the change in potential of the auxiliary capacitance line is stored, so that the influence increases when data are written on the next block (see FIG.
6
).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a flat display unit capable of obtaining a good display screen.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, a flat display unit comprises: a display area including a plurality of scanning lines, a plurality of signal lines, a plurality of switching elements, each of which is arranged in the vicinity of each of the intersections of the scanning lines and the signal lines, and a plurality of display pixels, each of which is connected to a corresponding one of the switching elements, the display area being divided into a plurality of small regions, each of which includes a set of signal lines of the plurality of signal lines; and a plurality of signal line driving circuits, each of which is arranged so as to correspond to a corresponding one of the small regions, for supplying a picture signal to each set of signal lines in parallel, at least one of the plurality of signal line driving circuits comprising: a shift register for transferring a start pulse in a predetermined direction in a predetermined timing; a sampling circuit for sampling an input picture signal to supply the picture signal to a corresponding one of the signal lines on the basis of an output of each stage of the shift register; and a control circuit for inverting the transfer direction of the start pulse every a predetermined time.
The transfer direction of the start pulse in one of adjacent two of the plurality of small regions may be the reverse of that in the other small region during the same period.
The predetermined period may be one horizontal scanning period in which a selecting voltage is applied to one of the plurality of scanning lines.
The sampling circuit may be integrally formed on a substrate constituting the flat display unit.
According to a second aspect of the present invention, a flat display unit comprises: a display area including a plurality of scanning lines, a plurality of signal lines, a plurality of switching elements, each of which is arranged in the vicinity of each of the intersections of the scanning lines and the signal lines, and a plurality of display pixels, each of which is connected to a corresponding one of the switching elements; a shift register for transferring a start pulse in a predetermined direction in a predetermined timing; a sampling circuit for simultaneously sampling a plurality of input picture signals to simultaneously supply the picture signals to a correspondin

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