Semiconductor memory device having high-speed read function

Details Semiconductor memory device having high-speed read function Semiconductor memory device having high-speed read function

2000-11-28

2002-10-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010

Reexamination Certificate

active

06466508

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device conducting a high-speed page-mode read operation.
2. Description of the Background Art
With improvement in performance of microprocessors and the like, semiconductor memory devices including random access memories (RAMs) have been strongly required to have both increased capacity and speed.
FIG. 16
is a schematic block diagram showing the structure associated with the read operation of a conventional typical semiconductor memory device.
Referring to
FIG. 16
, a conventional semiconductor memory device
100
includes a memory cell array
10
having a plurality of memory cells arranged in a matrix. For example, memory cell array
10
is divided into eight data blocks DB
0
to DB
7
. Note that, hereinafter, each data block DB
0
to DB
7
is sometimes generally referred to as data block DB.
An address signal Add used for address selection in memory cell array
10
is input from the outside as a 16-bit signal of address bits A
0
to A
15
. The address bits A
0
to A
9
of the address signal Add select a memory cell row, whereas the address bits A
10
to A
15
select a memory cell column. A row address buffer
20
receives the address bits A
0
to A
9
used for row selection. A column address buffer
30
receives the address bits A
10
to A
15
used for column selection.
Row address buffer
20
and column address buffer
30
produce an internal address signal Add corresponding to the externally input address bits A
0
to A
15
. The internal address signal Add has internal address bits a
0
to a
15
. The internal address bits a
0
to a
9
are transmitted to a row decoder
40
, whereas the internal address bits a
10
to a
15
are transmitted to a column decoder
50
.
Row decoder
40
selectively activates a word line WL (not shown) provided for each memory cell row, according to the internal address bits a
0
to a
9
. Thus, a memory cell row according to the internal address bits a
0
to a
9
is selected in each data block DB.
In each data block, m bit lines BL (not shown) are provided corresponding to the respective memory cell columns (where m is a natural number).
Semiconductor memory device
100
further includes column selection circuits YG
0
to YG
7
and sense amplifier circuits SA
0
to SA
7
provided corresponding to the respective data blocks DB
0
to DB
7
. Note that, like data block DB, each sense amplifier circuit and each column selection circuit are hereinafter sometimes generally referred as sense amplifier circuit SA and column selection circuit YG, respectively.
Each column selection circuit YG selects a single bit line BL in the corresponding data block DB according to the internal address bits a
10
to a
15
, and couples that bit line BL to the corresponding sense amplifier circuit SA. For example, column selection circuit YG
0
selects one of the m bit lines BL provided in data block DB
0
, and couples the bit line BL to sense amplifier circuit SA
0
.
Semiconductor memory device
100
further includes an address transition detection circuit (hereinafter, simply referred to as an ATD generation circuit)
60
. ATD generation circuit
60
receives the internal address bits a
0
to a
15
, and activates an address transition detection signal/ATD as one-shot pulse for a prescribed period when the signal level of at least one internal address bit is changed.
Each sense amplifier circuit SA conducts a bit-line precharging operation in response to activation of tie address transition detection signal/ATD. When the address transition detection signal/ATD is inactivated thereafter, the voltage on the precharged bit line changes according to the data stored in the memory cells connected to the bit line.
Sense amplifier circuits SA
0
to SA
7
sense such a change in voltage on the corresponding bit line, and outputs read data SD
0
to SD
7
, respectively. The read data SD
0
to SD
7
is transmitted to an output buffer
70
. Output buffer
70
buffers the read data SD
0
to SD
7
from sense amplifier circuits SA
0
to SA
7
, and outputs the data to the outside as output data D
0
to D
7
of semiconductor memory device
100
.
FIG. 17
is a diagram illustrating column selection in semiconductor memory device
100
.
Referring to
FIG. 17
, column selection circuits YG provided corresponding to the respective data blocks DB conduct m: 1 column selection. Each column selection circuit YG has m column selection switches YS
0
to YSm−1 provided corresponding to m bit lines BL
1
to BLm-1, respectively. Column selection switches YS
0
to YSm−1 are respectively turned ON in response to activation of column selection signals Y
0
to Ym−1. Column decoder
50
selectively activates one of the m column selection signals Y
0
to Ym−1 according to combination of the signal levels of the internal address bits a
10
to a
15
.
Each column selection circuit YG couples one of the m bit lines BL
1
to BLm−1 to the corresponding sense amplifier circuit SA. Sense amplifier circuit SA precharges that bit line in response to activation of the address transition detection signal/ATD, in order to read new data. The address transition activation signal/ATD is inactivated again after a prescribed period. Therefore, sense amplifier circuit SA senses a change in voltage caused by the memory cells connected to the precharged bit line, thereby outputting the read data SD.
FIG. 18
is a timing chart illustrating the read operation of semiconductor memory device
100
.
Referring to
FIG. 18
, addresses #A
0
to #A
6
are sequentially selected by the address signal Add. The address transition detection signal/ATD is activated in response to address transition. In response to respective activation of the address transition detection signal/ATD, sense amplifier circuits SA
0
to SA
7
conduct a new data read operation, thereby outputting read data groups #SD
0
to #SD
6
corresponding to the addresses #A
0
to #A
6
, respectively.
Output buffer
70
buffers the read data groups #SD
0
to #SD
7
, thereby outputting the output data groups #D
0
to #D
7
, respectively.
Current consumption of the read operation is given by the sum of a charging current Ich for charging the bit line in response to activation of the address transition detection signal/ATD, and a stationary current Ice consisting of a current steadily consumed by the sense amplifier and a memory cell current flowing into the memory cells upon reading the data.
In the conventional semiconductor memory device, the data reading speed is dependent on a memory cell current flowing into the memory cells upon reading the data, and a bit-line load for charging the bit line. Therefore, cell-size reduction for increased capacity and increase in data reading speed are opposed to each other, whereby the increase in data reading speed has been limited.
Such a problem is conventionally overcome by the page-mode reading. In general, the page-mode reading is a read operation in which a plurality of memory cells are accessed by sequentially changing the column while the row selection is fixed.
Fig
19
is a schematic block diagram showing the structure associated with the read operation of a conventional semiconductor memory device
110
for conducting the page-mode read operation at 2 bytes/page.
Referring to
FIG. 19
, in semiconductor memory device
110
, each data block DB
0
to DB
7
is divided into two sub data blocks in order to conduct the page-mode reading. For example, data block DB
0
is divided into two sub data blocks SDB
0
a
and SDB
0
b
. Note that, hereinafter, each sub data block is sometimes generally referred to as sub data block SDB.
Moreover, one of the two sub data blocks of each data block, i.e., SDB
0
a
to SDB
7
a
, is hereinafter sometimes generally referred to as sub data block SDBa, whereas the other of the two sub data blocks of each data block, i.e., SDB
0
b
to SDB
7
b
, is sometimes gener

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