Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-06-08
2002-10-22
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S718000, C324S719000, C438S004000, C438S010000, C438S014000, C438S017000
Reexamination Certificate
active
06469535
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for evaluating the surface state of a semiconductor substrate during a fabrication process of semiconductor devices and to a method for controlling the fabrication process of semiconductor devices based on the results of evaluation.
An “I-V method” is known as an exemplary technique for evaluating the surface state of a semiconductor substrate. In the I-V method, a metal electrode, which forms a Schottky barrier with a semiconductor substrate, is brought into contact with the substrate, and a voltage is applied between the substrate and the electrode to measure the amount of current flowing therebetween. Based on the resulting variation in current with the voltage applied, the surface state of the semiconductor substrate is evaluated according to this technique.
FIG. 18
is a schematic illustrating a measuring principle of this I-V method. As shown in
FIG. 18
, an Si substrate
1
, which is a target of measurement, is placed on a stage
2
of this measuring system. And a mercury electrode
3
, which forms a Schottky barrier with the Si substrate
1
, is in contact with the surface of the Si substrate
1
. A variable voltage is applied from a voltage supply
16
between the Si substrate
1
and the mercury electrode
3
. And the resultant current and voltage are measured with an ammeter
17
and a voltmeter
5
, respectively.
Hereinafter, results of I-V evaluation on the surface state of the semiconductor substrate
1
, which was exposed to a plasma of the type increasing a contact resistance, will be described. In this case, an n-type silicon wafer, of which the surface is a (
100
) crystallographic plane and the resistivity is 10 &OHgr;·cm, was used as the Si substrate
1
. A parallel-plate reactive ion etching (RIE) system was used to form a region with plasma-induced damage (hereinafter, simply referred to as a “damaged layer”). A mixed gas of CHF
3
and O
2
was used as an etching gas, the pressure of the gas was set at 5 Pa, and a radio frequency power of 1 kW was applied at 13.56 MHz. Under these conditions, a damaged layer was formed within the Si substrate
1
, which was then subjected to an O
2
down-flow plasma ashing process, and an organic compound deposited on the Si substrate
1
was removed therefrom. Subsequently, the Si substrate was subjected to down-flow etching within a plasma ambient using a mixed gas of CF
4
and O
2
, thereby partially removing a surface region of the Si substrate
1
to a depth of 5 to 60 nm. During this down-flow etching (also called “chemical dry etching (CDE)”), the pressure of the gas was 133 Pa and an RF power of 300 W was applied at 13.56 MHz. With such CDE etching, since part of a semiconductor substrate is going to be removed by a chemical action almost without receiving the impact of plasma ions, no damaged layer is newly formed within the semiconductor substrate.
Thereafter, the Si substrate
1
was subjected to ashing with O
2
plasma, cleaning with H
2
SO
4
and H
2
O
2
and cleaning with diluted HF. Then, using the arrangement shown in
FIG. 18
, a variable voltage was applied between the mercury electrode
3
and the Si substrate
1
to measure resulting current and voltage by the ammeter
17
and voltmeter
5
, respectively.
FIG. 19
illustrates data on the current-voltage characteristics obtained by this measurement. In
FIG. 19
, a curve indicated by “control” shows data on a bare silicon substrate
1
, which was not subjected to either RIE or CDE. As shown in
FIG. 19
, in a substrate that was etched by the CDE technique to a depth as small as 5 nm, the resulting current was small and the current-voltage characteristics were disturbed. Accordingly, it is estimated that a lot of damage would have remained in such a substrate. It is also understood that some samples, which were supposed to show Schottky properties, actually show ohmic properties. Furthermore, even a bare silicon substrate showed ohmic properties if the substrate had been subjected to the CDE process. Thus, it is suggested that some change would have been caused in the surface state of the Si substrate as a result of the CDE process.
Next, supposing that any CDE-etched sample showed a similar variation in its surface state, RIE-induced damage in a CDE-etched sample was evaluated.
FIG. 20
illustrates a variation in current with an etch depth where a voltage applied is −0.2 V in the I-V characteristic curves shown in
FIG. 19
, to show in detail how the damage recovers in a CDE-etched sample. As shown in
FIG. 20
, when the etch depth is 40 nm, the current abruptly increases. In other words, it can be understood that the damaged layer reaches a depth of 40 nm as measured from the surface of the Si substrate
1
.
As can be understood from the foregoing description, the depth of a damaged layer, which has been formed within a plasma-processed Si substrate
1
, can be known during the fabrication process by utilizing the conventional I-V method. Accordingly, even if no devices such as transistors have been formed yet on the Si substrate
1
, the surface state of the Si substrate
1
can be evaluated almost non-destructively. And based on the results of evaluation, it can be determined whether or not the plasma processing conditions should be changed and whether or not the process should proceed to the next step.
The conventional I-V evaluating method, however, has the following drawbacks.
FIG. 5
illustrates a resulting variation in contact resistance with a CDE etch depth of an Si substrate, which had been examined in the above-described manner and on which an AlSiCu interconnect had been formed. As shown in
FIG. 5
, even in the damaged Si substrate, when the depth of the etched part of the substrate reaches 3 nm, the contact resistance has decreased drastically. And when the etch depth reaches 8 nm, the contact resistance is almost zero. In other words, the increase in contact resistance due to the damage can be eliminated on and after the etch depth reaches 8 nm as measured from the surface of the Si substrate according to the results shown in FIG.
5
. But the results shown in
FIG. 5
are contradictory to those of the conventional I-V evaluation shown in FIG.
20
. According to the conventional I-V evaluation, damage can be detected with sufficiently high sensitivity. However, in accordance with the I-V evaluation, subtle defects, which are located much deeper than the damaged layer to be actually removed, are also detected unnecessarily. That is to say, although some of the damages, which are located at a depth of 40 nm as shown in
FIG. 20
, may have no impact on the performance of semiconductor devices, the conventional I-V evaluation defines the etch depth at 40 nm. As a result, overly excessive etching is performed unintentionally, because 40 nm is much deeper than an actually required depth of 8 nm.
Accordingly, in actuality, the results of conventional I-V evaluation on the depth of the damaged layer were not applicable in an “in-line” fashion (or between processing steps of a fabrication process) to the determination of an etch depth for the purpose of removing the damaged layer. Thus, in practice, the depth of the damaged layer to be removed was determined empirically by measuring a contact resistance after interconnection had been formed.
SUMMARY OF THE INVENTION
An object of the present invention is providing respective methods for examining a semiconductor substrate and controlling a fabrication process of semiconductor devices, which contribute to various determinations during the fabrication process, by taking measures to evaluate the surface state of a plasma-processed semiconductor substrate with no interconnects formed thereon.
To achieve this object, according to the present invention, the surface state of a semiconductor substrate is evaluated by analyzing an electrical phenomenon resulting from a trapping change in the interface between the substrate and a measuring terminal placed thereon. For example, either a variation in current with a constant voltage
Egashira Kyoko
Eriguchi Koji
Hamdan Wasseem H.
Nixon & Peabody LLP
Studebaker Donald R.
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