Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-02-14
2002-11-05
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C361S772000
Reexamination Certificate
active
06476331
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention includes a printed circuit board for a semiconductor package and related methods and structures.
2. Description of the Related Art
In the market for semiconductor packages, there is a trend toward ever smaller, more efficient, higher capacity, and less expensive packages with excellent heat transfer capabilities and electrical properties. Consistent with such trends, semiconductor packages today are often made to have an internal printed circuit board substrate, rather than a metal leadframe substrate.
A conventional single-layered printed circuit board
100
′ is shown in
FIGS. 7
a
and
7
b
. Thin copper circuit patterns
4
are formed on opposing upper and lower surfaces
2
a
,
2
b
of a resin layer
2
. A chip mounting section
12
is formed on a center portion of upper surface
2
a
of resin layer
2
. The circuit patterns
4
on the upper and lower surfaces
2
a
,
2
b
of the resin layer
2
are electrically connected with each other by conductive via-holes
10
through resin layer
2
. The circuit patterns
4
on upper surface
2
a
of resin layer
2
include bond fingers
4
a
, which are ultimately electrically connected to a semiconductor chip (not shown) provided on chip mounting section
12
. The circuit patterns
4
on lower surface
2
b
of resin layer
2
include ball lands
4
b
to which conductive balls are ultimately fused. The entire areas of the upper and lower surfaces
2
a
and
2
b
and circuit patterns
4
, excluding bond fingers
4
a
and ball lands
4
b
, are coated with a protective solder mask
8
. Plating layer
6
is formed on the bond fingers
4
a
and ball lands
4
b
of the circuit patterns
4
by an electroplating technique using nickel (Ni) and gold (Au) so as to facilitate the subsequent bonding of conductive wires and conductive balls thereto, respectively. Singulation holes
14
provide a reference for a singulation process that severs the circuit board strip. Index holes
16
provide a reference for loading the printed circuit board
100
′ on automated manufacturing equipment.
A method for manufacturing printed circuit board
100
′ includes providing a resin layer
2
that has a copper film layer laminated on its upper and lower surfaces. Subsequently, holes are formed through resin layer
2
and the copper film layers. A metal coating is provided on the circumferential inner wall surfaces of certain of the holes to form via-holes
10
, thereby electrically connecting the upper and lower copper film layers. Chip mounting section
12
and circuit patterns
4
, including the bond fingers
4
a
and ball lands
4
b
, are formed by patterning the copper film layers. The chip mounting section
12
, the circuit patterns
4
(except for bond fingers
4
a
and ball lands
4
b
), and the areas of upper and lower surfaces
2
a
,
2
b
surrounding the circuit patterns
4
are coated with a solder mask
8
, which may be a polymer resin. Finally, the bond fingers
4
a
and ball lands
4
b
are electroplated with sequential layers of nickel (Ni) and gold (Au).
However, in making such a printed circuit board, in order to conduct the electroplating technique, the circuit patterns
4
must necessarily extend to peripheral edges of the printed circuit board, as shown in
FIG. 7
a
. Because the circuit patterns
4
must be provided at the periphery of the printed circuit board to allow the electroplating to be conducted, it is difficult to freely design a dense and fine arrangement of the circuit patterns
4
.
Moreover, bond fingers
4
a
are plated on their vertically extending peripheral side surfaces
5
a
(which are substantially perpendicular to the underlying surface of resin layer
2
), as well as on their outer horizontal surfaces
5
b
, which are parallel to the underlying surface of resin layer
2
. This plating on the peripheral side surfaces
5
a
bond fingers
4
a
reduces an adhesion force between bond fingers
4
a
and an encapsulating material subsequently applied over the circuit board
100
′ (including bond fingers
4
a
) and over the semiconductor chip.
To cope with such difficulties, another printed circuit board manufacturing method, which is known as a full body gold (FBG) plating method, may be used. Referring to printed circuit board
100
″ of
FIGS. 8
a
and
8
b
, circuit patterns
4
of the printed circuit board were plated using the FBG method. The circuit patterns do not extend to the peripheral edges of the printed circuit board
100
″. Accordingly, a peripheral region of the upper and lower surfaces
2
a
,
2
b
of resin layer
2
around printed circuit board
100
″ is free of circuit patterns
4
.
In the FBG manufacturing method, a plating layer
6
each having a predetermined thickness is formed in advance by electroplating nickel (Ni) and gold (Au) on predetermined regions of an unpatterned copper layer on the upper and lower surfaces of the resin layer
2
. The plated regions correspond to the circuit patterns
4
that are to be formed later from the thin copper film layers. Thereafter, the upper and lower copper film layers are etched using the plating layers
6
as masks, thereby removing unnecessary portions of the copper film layers, and forming circuit patterns
4
that are plated over their entire outer horizontal surface
5
b
, including portions other than bond fingers
4
a
or ball lands
4
b
. Then, a solder mask
8
is coated on the upper and lower circuit patterns
4
in a manner such that the previously-plated bond fingers
4
a
and ball lands
4
b
are exposed to the outside.
However, the FBG-plated printed circuit board still suffers from defects in that, since the adhesion force between the solder mask
8
and the plating layer
6
is weak, the solder mask
8
can be easily stripped off from the circuit patterns
4
. Accordingly, the operational reliability of the printed circuit board
100
″ can be seriously deteriorated. Further, since nickel (Ni) and gold (Au) are unnecessarily provided on portions of the horizontal outer surface
5
b
of the circuit patterns
4
other than bond fingers
4
a
and ball lands
4
b
, the cost to make printed circuit board
100
″ is unnecessarily high.
SUMMARY OF THE INVENTION
The present invention provides, among other things, a printed circuit board for a semiconductor package and a method for manufacturing the same. The present invention allows a highly integrated design of circuit patterns on the printed circuit board with improved reliability and cost savings by comparison to the conventional art described above.
One embodiment of a printed circuit board for a semiconductor package in accordance with the present invention includes a core layer having conductive circuit patterns formed thereon. The circuit patterns include (individually or collectively) bond fingers and ball lands. A solder mask is coated on the circuit patterns, except over the bond fingers and ball lands. A metal plating layer is provided only on the outer horizontal surfaces of the bond fingers, and not on other horizontal outer or side surfaces of the circuit patterns outside the bond fingers. The circuit patterns do not extend to an outer periphery of the circuit board. Accordingly, a complicated and dense layer of circuit patterns can be provided on the board, stripping of the solder mask from the circuit patterns can be avoided, waste of the plating metal is avoided, and adhesion between an encapsulant and the bond fingers can be enhanced.
The present invention also includes, among other things, a semiconductor package made with the various printed circuit boards of the present invention, and methods of making such packages.
The above and other aspects and features of the present invention will become more apparent from the detailed description and drawings of the exemplary embodiments.
REFERENCES:
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5386342 (1995-01-01), Rostoker
patent: 5397917 (1995-03-01), Ommen et al.
patent: 5436411 (1995-07-01), Pasch
patent: 54
Kim Sung Jin
Son Sun Jin
Amkor Technology Inc.
Paladini Albert W.
Parsons James E.
Skjerven Morrill LLP
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