Silicon carbide junction field effect transistor

Details Silicon carbide junction field effect transistor Silicon carbide junction field effect transistor

2000-07-11

2002-04-02

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S261000, C257S259000, C257S266000, C257S269000, C257S279000, C257S256000

Reexamination Certificate

active

06365919

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed to a silicon carbide junction field effect transistor (FET). Specifically, the invention relates to a field effect transistor having a silicon carbide body in which p-conductive and n-conductive layers are present, and having source, drain and gate electrodes.
2. Description of Related Art
Silicon carbide junction field effect transistors can be utilized as high-voltage components in, for example, cascade circuits. They have the advantage that they can be manufactured with comparatively little outlay since dopings therein can be implanted with little difficulty.
Up to now, however, there have only been vertical structures for silicon carbide junction field effect transistors. The integration of these vertical structures is problematical due to the drain electrode being placed at the back side of the silicon carbide body.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to specify a silicon carbide junction field effect transistor having lateral structure that is simple to manufacture and that is distinguished by a high high-voltage strength.
In an embodiment, the present invention provides a silicon carbide junction filed effect transistor that includes a silicon carbide body having a principal surface. A plurality of p-conductive and n-conductive layers are embedded in pairs in the silicon carbide body in a lateral direction parallel the principal surface. At least two trenches are in the silicon carbide body as a source and a drain, respectively, and penetrate the n-conductive and p-conductive layers, the trenches are filled with highly doped silicon carbide that is either a n-conductive or p-conductive type. A third trench is a gate electrode that extends from the principal surface and penetrates the n-conductive and p-conductive layers. The third trench has an insulating layer at an edge of the third trench. The third trench is filled with a conductivity type that is opposite to the conductivity type of the at least two trenches.
It is provided in a development of the invention that the doping concentration of the p-conductive and n-conductive silicon carbide layers is not higher than 10
13
charge carrier/cm
2
. It is also advantageous that the trenches for the source and gate electrodes at least partially surround the trench for the drain electrode. The n-conductive and p-conductive silicon carbide layers can be produced by ion implantation and epitaxial deposition on a silicon carbide base member.
The invention thus creates a silicon carbide junction field effect transistor in lateral structure that can be manufactured with little difficulty and with currently available means.
Thus, non-doped, epitaxial layers that form an epi structure are deposited on a non-doped silicon carbide base member. N-conductive and p-conductive silicon carbide layers are enclosed in pairs in this epi structure, these being produced with ion implantation of n-conductive or, respectively, p-conductive dopants such as, nitrogen or, respectively, boron and/or aluminum. The uppermost layer of this epi structure remains undoped.
Narrow trenches are then etched into the epi structure. Then the trenches are epitaxially filled with, for example, n
+
-doped silicon carbide for the source electrode and the drain electrode and with p
+
-doped silicon carbide for the gate electrode after deposition of an insulating layer. The n
+
-conductivc and p
+
-conductive silicon carbide layers thus applied in the trenches for source, drain and gate are finally etched back to the uppermost, undoped silicon carbide layer and are structured in this way.
Advantageously, a geometry can be selected for the electrodes wherein the trenches for the source electrode and the gate electrode surround the drain electrode.
The metallization of the silicon carbide junction field effect transistor can ensue in a standard way. It is an advantage that the interconnects of, for example, aluminum or of polycrystalline silicon can be utilized.
The doping concentration in the p-conductive or n-conductive silicon carbide layers should expediently not exceed 10
13
cm
−2
. What this upper limitation achieves is that the p-conductive and n-conductive silicon carbide layers are cleared earlier in lateral or, respectively, transverse direction as a result of this upper limitation before a punch-through occurs, so that the silicon carbide junction field effect transistor is then distinguished by a high breakdown resistance. In other words, the inventive silicon carbide junction field effect transistor has a high breakdown voltage given a low turn-on impedance.
The invention is explained in greater detail below with reference to the drawings.


REFERENCES:
patent: 3254280 (1966-05-01), Wallace
patent: 5378642 (1995-01-01), Brown et al.
patent: 5465249 (1995-11-01), Cooper, Jr. et al.
patent: 5679966 (1997-10-01), Baliga et al.
patent: 196 44 821 (1998-02-01), None
S. Sriram et al., “RF Performance of SiC MESFET's on High Resistivity Substrates”, IEEE Electron Device Letters, vol. 15, No. 11, Nov. 1994, pp. 458-459.
Levinshtein et al., “Nature of the 1/f noise in 6H-SiC”, Semiconductor Science and Technology, pp. 2080-2084.

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