Power drive circuit

Details Power drive circuit Power drive circuit

2000-12-05

2002-04-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S424000, C327S588000, C327S112000

Reexamination Certificate

active

06369638

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a balanced transformer-less (BTL) power drive circuit for use in a disk drive system for a CD, a CD-ROM, and an MD for example.
BACKGROUND OF THE INVENTION
Many of disk drive systems for CDs, CD-ROMs, and MDs employ a BTL power drive circuit.
FIG. 1
shows a push-pull type power drive circuit for use in a BTL power drive circuit having two such push-pull drive circuits.
As shown in
FIG. 1
, an NPN output transistor Q
1
and an NPN output transistor Q
2
are connected in series between a main power supply having an electric potential PowVcc and the ground of potential E. The node of the transistors Q
1
and Q
2
is connected to the output terminal of the circuit for provision of an output potential Vout. Connected between the base and the emitter of the transistor Q
1
is a resistor R
1
, and connected between the collector and the base of the transistor Q
2
are a PNP transistor Q
4
and a capacitor C
1
, and is a resistor R
2
between the base and the emitter of the transistor Q
2
. The output terminal OUT is also connected, via a resistor R
5
, to a node having a reference output potential Vref (which will be hereinafter referred to as internal reference potential Vref).
When an input signal Vin is supplied to the input terminal IN of a pre-buffer section (hereinafter referred to as pre-buffer circuit) B
1
serving as an input control section of the power drive circuit. An PNP transistor Q
3
of the pre-buffer circuit B
1
provides its output signal to the bases of the transistors Q
1
and Q
2
, under the control of the input signal Vin.
The pre-buffer circuit B
1
further includes PNP transistors Q
5
and Q
6
, and NPN transistors Q
7
and Q
8
, resistors R
3
, R
4
, and R
6
, a diode D
1
, and constant current sources I
1
, I
2
, and I
3
, as shown in FIG.
1
.
The input signal Vin shown in
FIG. 1
is formed by an input signal and an internal reference potential Vref in a pre-stage difference amplifier circuit (not shown) which is driven by the potential PowVcc of the main power supply PowVcc. In other words, a DC potential arising from the main power supply potential PowVcc is superposed on the input signal Vin at the input terminal IN.
When no signal is supplied to the power drive circuit shown in
FIG. 1
, i.e. the level of the input signal Vin is zero, the level of the output potential Vout of the circuit is equal to the internal reference potential Vref. Since the NPN output transistors Q
1
and Q
2
are controlled by the input signal Vin, the output potential Vout is swung accordingly in the positive
egative direction about the internal reference potential Vref as the input signal Vin deviates from zero in the positive
egative direction.
The upper limit of the output potential Vout of the power drive circuit is defined by the saturation voltage Vsat of the PNP output transistor Q
3
and by the forward base-emitter potential drop Vf of the NPN output transistor Q
1
, so that the upper limit will be [PowVcc−Vsat−Vf]. Similarly, the lower limit of the output potential Vout is defined to be the saturation voltage Vsat of the NPN output transistor Q
2
.
Consequently, the width of the dynamic range of the output potential Vout will be [PowVcc−2Vsat−Vf], with the internal reference potential Vref set to the medium [(PowVcc−Vf)/2].
FIG. 2
shows a BTL power drive circuit comprising of two push-pull type power drive circuits as shown in
FIG. 1
, where components in one power drive circuit that correspond to the counterparts in the other power drive circuit are denoted with primes (′). It is noted that a load L is connected between the output terminal OUT of one power drive circuit and the output terminal OUT′ of the other power drive circuit, and that an inverted input signal {overscore (Vin)}, which is the inversion of the input signal Vin, is applied to the input terminal {overscore (IN)} of the other power drive circuit.
In the BTL power drive circuit of
FIG. 2
, the output potentials Vout and Vout′ of the output terminals OUT and OUT′, respectively, are swung in the opposite directions with respect to the internal reference potential Vref in response to the input signal Vin, so that the dynamic range of the output potential Vout is double that of the power drive circuit of
FIG. 1
, thereby providing a doubly large driving power for the load.
However, in the power drive circuit of FIG.
1
and hence in the BTL power drive circuit of
FIG. 2
, the upper limits of the output potential Vout and Vout′ are limited by the saturation voltage Vsat of the PNP transistor Q
3
and the forward potential drop across the base-emitter of the NPN transistor Q
1
. The forward base-emitter potential drop Vf is substantially constant and has a dominant influence on the output voltage Vout and Vout′ as compared with the saturation voltage Vsat. Thus, in order to extend the dynamic range of a power drive circuit driven by a main power supply having a low potential PowVcc, it is desirable to remove the influence of the forward base-emitter potential drop Vf.
FIG. 3
shows a push-pull type power drive circuit which is an improvement of the power drive circuit of
FIG. 1
, in which dynamic range is extended by increasing the upper limit of the output potential Vout.
In
FIG. 3
, the main power supply of potential PowVcc is used as the power supply for the NPN output transistor Q
1
and the NPN output transistor Q
2
. In addition, a further auxiliary power supply of potential PreVcc is used as the power supply for the pre-buffer circuit B
1
that includes the PNP transistor Q
3
and other elements.
In a disk system such as a CD-ROM which includes a high-voltage power supply of 12 Volt in addition to an ordinary 5 Volt power supply, the high-voltage power supply may be used as the auxiliary power supply PreVcc.
In this instance, the pre-stage differential amplifier circuit which receives a pre-stage input signal and an internal reference potential Vref, is driven by the auxiliary power supply potential PreVcc. The input signal Vin is fed to the input terminal IN and is superposed on a DC potential arising from the auxiliary power supply PreVcc.
As described above, when the potential PreVcc of the auxiliary power supply is the same as that of the main power supply PowVcc, as shown in
FIG. 1
, the upper limit of the output potential Vout, is given by [PowVcc−Vsat−Vf], since the upper limit is given by the larger one of the saturation voltage Vsat of the NPN output transistor Q
1
and the sum of the saturation voltage Vsat of the PNP transistor Q
3
and the forward base-emitter potential drop Vf of the NPN output transistor Q
1
.
In contrast, the upper limit of the output potential Vout of the circuit of
FIG. 3
is given by the supply potential PowVcc of the main power supply minus the saturation voltage Vsat of the NPN output transistor Q
1
, [PowVcc−Vsat], since the upper limit is given by the smaller one of the auxiliary power supply potential PreVcc minus the saturation voltage Vsat of the PNP transistor Q
3
and the forward base-emitter potential drop Vf of the NPN output transistor Q
1
, and the potential of the main power supply PowVcc minus the saturation voltage Vsat of the NPN output transistor Q
1
. Thus, the dynamic range of the drive circuit of
FIG. 3
is extended by the enlarged output potential Vout.
It should be noted that although the dynamic range is extended on one hand by the use of the auxiliary power supply having as high as 12 Volts in the circuit shown in
FIG. 3
, high energy consumption by the pre-buffer circuit B
1
is inevitable so long as the pre-buffer B
1
uses the auxiliary power supply.
It would be understood that a BTL power drive circuit having an extended dynamic range can be formed, as shown in
FIG. 4
, using two power drive circuits shown in
FIG. 3
having an extended upper limit of the output potential Vout. The BTL power drive circuit as shown in
FIG. 4
has basically

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