Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-07-05
2002-09-17
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C029S846000, C029S847000, C204S157150, C427S508000, C427S510000
Reexamination Certificate
active
06452110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit storage devices and more particularly to an improved method for producing electrically conductive embedded lines in an insulating dielectric layer.
2. Description of the Related Art
An integrated circuit, or any other semiconductor device is constructed to have several electronic circuit elements interwoven on a single body of semiconductor material. The various circuit elements, such as amplifiers, conductors, diodes, resistors, and transistors, to name a few, are integrated through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Technological advances in semiconductor material selection and other processing techniques have resulted in allowing for an increased number of individual circuit elements on a single semiconductor body, while reducing the overall size of the individual circuit elements. This reduction in overall size yields a reduction in costs, yet an improvement in the integrated circuit performance.
The manner in which the various circuit elements communicate with one another is accomplished by interconnects, which provide the electrical connections between each element of the semiconductor device. Moreover, these interconnect lines form the connections between the internal circuit elements and the semiconductor's external contact elements, such as pins, for connecting the integrated circuit to other integrated circuits or devices. Generally, a mesh of layered connections results from the interconnect lines, which form the horizontal connections between internal circuit elements, and the conductive via plugs, which form the vertical connections between the internal circuit elements.
One method for producing these interconnect micron and sub micron metallic conducting lines embedded in an insulating dielectric layer is called a damascene process, with the resulting structure called a damascene structure. This structure and process are very well known to those skilled in the art. A damascene process is one kind of interconnect process. In a typical damascene process, a trench is formed in a dielectric layer. Then, a metal layer is formed in the trench to form a conductive line as an interconnect. Similarly, a dual damascene process is one type of multilevel interconnect process. Here, a contact or a via is additionally formed as an interconnect.
Usually, in a conventional damascene process, a dielectric layer is formed over a semiconductor substrate. In some processes an oxide layer is formed on top of the dielectric layer. Then, a chemical-mechanical polishing (CMP) process is performed to planarize the dielectric layer. Next, a patterned photoresist layer is formed on the dielectric layer. Thereafter, using the photoresist layer as a mask, the dielectric layer is etched by dry etching to form a trench in the substrate. At this time, the photoresist layer is removed, perhaps by oxygen plasma. Next, metal liner and seed layers are deposited, followed by another metallization process to completely fill the lines. Finally, a metal CMP process is performed to remove the excess metal from the areas between the trenches leaving conducting metal in the trenches. In dual and other multiple damascene processes, the number of dielectric layers are multiplied, whereby the number of mask layers are correspondingly added. These processes are rather complex and require many more processing steps to complete. The prior art damascene process has the disadvantage of requiring etching of the insulating layer and/or requiring multiple metalization deposition steps contrary to the current disclosure. As indicated above, the prior art damascene structures are created with numerous processing steps.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional damascene process the present invention has been devised, and it is an object of the present invention to provide an alternative simplified methodology for the formation of an electronic interconnect structure relative to the traditional damascene approach of the prior art. This simplified method will provide a low-cost means for microfabrication manufacturing. The present method is simplified relative to prior art, in one respect, because there are fewer fabrication steps.
Another object of this invention is to create a planar structure of a patterned conductive polymer. A planar structure is desired in order to improve the patterning lithographic steps for subsequent fabrication processes by making a large depth-of-focus margin for exposure by the elimination of on-chip step height differences.
Still another object of this invention is to produce a method and structure for a self-planarizing interconnect material comprised of a conductive polymer. The polymer will self-planarize during a spin-on deposition. The self-planarizing aspect of the conductive polymer will result in a reduced number of fabrication process steps relative to the prior art, and will result in an improved depth-of-focus margin for subsequent lithographic patterning steps.
Yet another object of the present invention is to provide a method for the microfabrication of conductive elements comprised of photosensitive conductive polymer materials.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention an alternative methodology for a damascene process. The present invention provides for a novel “cloisonne” or “inverse damascene” approach. In the cloisonne approach, the use of a photosensitive conducting polymer, which acts as both a masking and conducting layer, is employed. The advantage of the cloisonne approach is that it takes fewer processing steps to end up with a similar final structure produced by the damascene approach. Consequently, this reduction of processing steps reduces processing time and reduces overall costs in semiconductor manufacturing.
More specifically, the cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Then, using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, which removes a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish (CMP) planarization of the insulator is performed creating the conducting polymer lines. Another aspect of the present invention involves a method and structure for a self-planarizing interconnect material comprising a conductive polymer, thereby reducing the number of processing steps relative to the prior art. Here, the method for producing metallic polymer conductor lines comprises the steps of depositing a self-planarizing conductive polymer material on a substrate using a spin-on application, and then patterning the conductive polymer material using either lithographic and dry etch techniques or by exposing a photosensitive component of the conductor polymer.
In the current disclosure, damascene structures are created with far fewer processing steps. Basically, with the present invention, a photosensitive conducting polymer film is deposited on a substrate. The conductor is then exposed and developed for forming conducting lines. An insulating layer is then deposited and polished by CMP back to the conducting polymer, resulting in an inverse damascene structure.
REFERENCES:
patent: 6021050 (2000-02-01), Ehman et al.
patent: 6210537 (2001-04-01), Murphy et al.
patent: 402273926 (1990-11-01), None
patent: 407058439 (1995-03-01), None
Clevenger Lawrence A.
Hon Wong Keith Kwong
Hsu Louis L.
Radens Carl J.
Wang Li-Kong
International Business Machines - Corporation
McGinn & Gibb PLLC
Paladini Albert W.
Underweiser, Esq. Marian
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