Sub-package bypass capacitor mounting for an array packaged...

Details Sub-package bypass capacitor mounting for an array packaged... Sub-package bypass capacitor mounting for an array packaged...

1999-04-05

2002-06-04

Gandhi, Jayprakash N. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S734000, C361S761000, C361S768000, C361S780000, C361S782000, C361S783000, C361S808000, C361S818000, C174S262000, C257S698000, C257S724000, C257S728000, C333S012000, C438S125000, C029S831000, C029S832000

Reexamination Certificate

active

06400576

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to providing integrated circuits (“ICs”) with better broadband low impedance power feed than is possible with conventional IC bypass capacitor placement, and more particularly for effectiveness of bypass capacitors used with land grid array (“LGA”) or pin grid array (“PGA”) packaged high pin density ICs.
2. Related Art
Integrated circuits commonly include a number of metal-oxide-semiconductor (“MOS”) transistors, bipolar transistors, diodes and/or other devices fabricated on a semiconductor substrate die that may ultimately be encapsulated within a protective package. Some nodes within the IC require external power supply voltages, ground, and signal connections. Such nodes are coupled within the encapsulation to IC pads to which with solder balls, pads, or the like may be attached. In this fashion, externally provided voltages and signals are coupled to the IC.
FIG. 1
, for example, depicts a socketed assembly
10
that includes an IC
20
with associated solder balls
30
-
1
,
30
-
2
. . .
30
-
10
mounted on a land grid array (“LGA”) package
40
, typically ceramic or a plastic material, depending upon ambient temperature specifications. The invention described later herein is also suitable for pin grid array (“PGA”) packages and as used herein, the term LGA will be understood to also include PGA.
The upper surface
50
of LGA package
40
will define a number of component conductive pads
60
-
1
, . . .
60
-
10
that make electrical connection to the IC package solder balls when IC
20
is mounted to the LGA package, e.g., by soldering. Within LGA package
40
conductive planes are formed such as Vcc plane
70
used to carry operating potential Vcc, and Vss plane
80
used to carry a reference potential Vss that is often ground. LGA package
40
may include more than two conductive planes
70
,
80
and typically will have a thickness (measured between surfaces
50
and
110
) in the range of perhaps 1 mm to 6 mm. The length and width of the LGA package may be 50 mm×50 mm or larger.
Vertically formed electrically conductive vias such as
90
-
1
,
90
-
4
,
90
-
5
,
90
-
10
are formed within package
40
. These vias permit chosen component conductive pads
60
-
1
,
60
-
4
,
60
-
5
,
60
-
10
on surface
50
of LGA
40
to make desired electrical connection to Vcc plane
70
, or Vss plane
80
, and/or LGA mounting pads
100
-
1
,
100
-
4
,
100
-
5
,
100
-
10
on lower surface
110
of LGA
40
. The fabrication of such vias is well known in the relevant art, and will not be described herein.
In
FIG. 1A
, solder balls
30
-
1
and
30
-
10
are coupled internally to nodes formed on IC
20
carrying input or output signals. Solder balls
30
-
1
and
30
-
10
make electrical connection to conductive pads
60
-
1
and
60
-
10
on the upper surface of the LGA package. In turn, these conductive pads make electrical contact respectively with vias
90
-
1
and
90
-
10
to respective LGA mounting pads
100
-
1
and
100
-
10
on the lower surface of the LGA package. Because vias
90
-
1
and
90
-
10
carry input or output signals, these vias pass through openings in planes
70
and
80
without making electrical contact to either plane.
Solder balls
30
-
4
and
30
-
5
are electrically coupled internally to nodes on IC
20
that require Vcc-and Vss potential, respectively. Thus, solder balls
30
-
4
and
30
-
5
are respectively electrically coupled to conductive pads
60
-
4
and
60
-
5
on the upper surface of the LGA package. Pad
60
-
4
is electrically coupled to Vcc plane
70
(but not to Vss plane
80
) with via
90
-
4
and to LGA mounting pad
100
-
4
on the lower surface
110
of the LGA package. Similarly pad
60
-
5
is electrically coupled to Vss plane
80
(but not to Vcc plane
70
) with via
90
-
5
and to LGA mounting pad
100
-
5
on the lower surface of the LGA package.
In use, LGA package
40
is inserted into an LGA socket
120
that is mounted to a motherboard or other substrate
130
that provides IC
20
with Vcc, Vss, and input and output signal access through socket contacts
140
-
1
,
140
-
4
,
140
-
5
,
140
-
10
. Socket
120
commonly is shaped as a rectangular or square frame with socket contacts including
140
-
1
,
140
-
2
, etc. located on the socket periphery. As such, a square or rectangular opening (or at least a recess)
150
is defined in the lower central portion of the socket.
In practice, IC
20
may include circuitry requiring relatively noise-free potential at Vcc and Vss component conductive pads
60
-
4
,
60
-
5
for reliable IC operation. By noise-free, it is meant that ideally signals at these pads should be pure DC, with essentially no AC transient components or crosstalk-coupled components. Some Ics are notorious for generating electrical noise. For example, high speed digital ICs exhibit rapid voltage and current transitions that can produce unwanted current surges and voltage spikes at the Vcc and Vss component conductive pads.
It is known in the art to reduce such noise on Vcc and Vss component conductive pads by coupling one or more bypass capacitors in shunt with these pads. Thus, in
FIG. 1
, it is common to dispose one or more bypass capacitors
160
,
170
on upper surface
50
of LGA
40
. The capacitors make electrical connection through solder balls (or the like)
30
-
20
,
30
-
21
,
30
-
22
,
30
-
23
to capacitor component conductive pads
60
-
20
,
60
-
21
, and
60
-
22
, and
60
-
23
, and then through vias
90
-
20
,
90
-
21
, and
90
-
22
,
90
-
23
to the Vcc plane
70
and the Vss plane
80
respectively. Ideally, each capacitor represents a low shunt impedance to high frequency transients, while representing a high shunt impedance to DC voltages.
Bypass capacitors
160
,
170
may be in the 0.1 &mgr;F range, depending upon the noise susceptibility characteristics of the IC(s) being bypassed. Typical dimensions for a conventional off-the-shelf 0.1 &mgr;F bypass capacitor are in the range of perhaps 6 mm×3 mm surface area, by 0.8 mm height.
Unfortunately, the mounting configuration for bypass capacitors
160
,
170
shown in
FIG. 1
is less than optimum to provide substantially noise-free signals for IC
20
at component conductive pads
60
-
4
,
60
-
5
. Simply stated, the horizontal and lateral electrical path lengths between the capacitors and the nodes being bypassed are too long, with the result that the effective (undesired) parasitic series inductance (Leff) is too large. Consider the path length from capacitor
160
to component conductive pad
60
-
4
. The height of via
90
-
22
may be a few mm, the lateral separation of via
90
-
22
from via
90
-
5
may be 30 mm, and the distance along via
90
-
5
upward to pad
60
-
5
will be a few mm, a total distance of perhaps 35 mm or more.
As shown in
FIG. 1B
, effective bypassing is compounded by the fact that at high frequencies, the Vcc, Vss conductive paths, e.g.,
70
,
80
, may themselves be equivalent to a distributed series of series-coupled parasitic resistor (R) and inductor (L) combinations with parasitic capacitance shunts (C) at the equivalent coupling nodes. Further, the various bypass capacitors, e.g.,
160
,
170
, have parasitic resistance Rs and inductance Ls coupled in series with the capacitor leads. In
FIG. 1B
, the connection linkage path from IC
20
to bypass capacitor
160
(or
170
) is shown with bold lines for emphasis. It will be appreciated that at high currents and/or high frequencies, L
1
, R
1
, C
1
, L
2
, R
2
, C
2
in the linkage paths, as well as Rs and Ls can degrade the effectiveness of the bypass capacitor
160
or
170
. A more detailed discussion of circuit models of parasitic components that can affect capacitor bypassing may be found in the treatise
Digital Systems Engineering
by W. J. Dally and J. W. Poulton, published by Cambridge University Press, especially portions of Chapter 5 therein.
The relatively long linkage path length between the bypass capacitor and an IC node to be bypassed, show

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