Heterojunction field effect transistor

Details Heterojunction field effect transistor Heterojunction field effect transistor

2000-01-27

2002-08-06

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S022000

Reexamination Certificate

active

06429467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a heterojunction field effect transistor (to be abbreviated as HJFET hereinafter) and, more particularly, an HJFET having good controllability for a threshold voltage.
2. Description of the Prior Art
FIG. 1A
is a view showing the element structure of an HJFET according to the prior art. This HJFET is reported in, e.g., U. K. Mishra et al, IEEE Transactions on Microwave Theory and Techniques, Vol. 46, page 756, 1998.
Referring to
FIG. 1A
, a buffer layer
91
comprised of a multilayered structure of aluminum nitride (AlN) and gallium nitride (GaN) is formed in contact with a sapphire (Al
2
O
3
) substrate
90
, and a channel layer
92
made of gallium nitride (GaN) is formed in contact with the buffer layer
91
. A gate insulating layer
93
made of undoped AlGaN is formed in contact with the GaN channel layer
92
. Two-dimensional electrons
94
are generated in the channel layer
92
to establish ohmic contact between a source electrode
97
S formed on the gate insulating layer
93
and a drain electrode
97
D, and the channel layer
92
. A gate electrode
99
is formed between the source electrode
97
S and drain electrode
97
D to establish Schottky contact with the gate insulating layer
93
.
FIG. 1B
is a schematic diagram of conduction band energy between the gate electrode
99
and GaN channel layer
92
of the prior art HJFET. The lattice constant (a-axis) of AlGaN forming the gate insulating layer
93
is shorter than that of GaN forming the buffer layer
91
. Hence, a piezoelectric field is formed to extend from the substrate toward the surface. Even when the gate voltage is 0 V, the two-dimensional electrons
94
are generated in the channel layer
92
. Therefore, in the prior art HJFET, the threshold voltage is difficult to control, and the prior art HJFET usually forms a depletion type FET. An enhancement type FET is thus difficult to fabricate.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems of the prior art, and has as its object to provide an HJFET structure that can form a depletion type FET and an enhancement type FET separately by improving the controllability for the threshold voltage.
In order to achieve the above object, according to the main aspect of the present invention, there is provided a heterojunction field effect transistor having a buffer layer including at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode on a substrate, wherein the channel layer has a composition of In
z
Ga
1−z
N (0≦z<1) and the gate insulating layer is an InAlGaN layer, and the source and drain electrodes are in ohmic contact with the channel layer and the gate electrode and the gate insulating layer are in Schottky contact with each other.
In the prior art, the threshold voltage is difficult to control due to the following reason. Namely, the lattice constant (a-axis) of AlGaN forming the gate insulating layer is shorter than that of GaN forming the buffer layer. Hence, two-dimensional electrons are generated in the channel layer due to a piezoelectric effect. To enable fabrication of a depletion type FET and an enhancement type FET separately by improving the controllability for the threshold voltage, the gate insulating layer may be made of a material the d-axis length of which can be changed around the lattice constant (a-axis) of GaN. This can be realized by setting, in In
x
Al
y
Ga
1−x−y
N as a four-element type semiconductor, the composition ratio of x to y appropriately.
In the present invention, in an HJFET having a GaN buffer layer and an In
z
Ga
1−z
N channel layer (0≦z<1), In
x
Al
y
Ga
1−x−y
N (x>0, y>0, x+y≦1) is used to form a gate insulating layer.
Even if In
z
Ga
1−z
N (z≠0) is used to form the channel layer, a good crystal free from crystal dislocation is formed at a small film thickness because of the effect of the strain layer. In this case, it is already known that the a-axis length of the In
z
Ga
1−z
N (z≠0) layer is equal to that of the GaN buffer layer. The thickness of the channel layer satisfying this condition is 300 Å or less and preferably 30 Å to 200 Å for z=0.1, and is 100 Å or less and preferably 30 Å to 80 Å for z=0.2.
The a-axis length of In
x
Al
y
Ga
1−x−y
N is expressed as:
a
(
x, y
)=3.548
x+
3.112
y+
3.189(1−
x−y
)Å  (1)
The condition under which the a-axis length of In
x
Al
y
Ga
1−x−y
N becomes smaller than that of the GaN buffer layer (a=3.189 Å) is: a(x, y)<3.189 Å. Hence,
y>
4.66
x
  (2)
At this time, a piezoelectric field is formed to extend from the substrate toward the surface, in the same manner as in the prior art, and accordingly a depletion type FET becomes easy to fabricate.
The condition under which the a-axis length of In
x
Al
y
Ga
1−x−y
N becomes larger than that of the GaN buffer layer is: a(x, y)>3.189 Å. Hence,
y<
4.66
x
  (3)
At this time, a piezoelectric field is formed to extend from the surface toward the substrate, unlike in the prior art. Hence, when the gate voltage is 0 V, the channel layer is depleted, and an enhancement type FET becomes easy to fabricate.
Preferably, the difference in the a-axis length between In
x
Al
y
Ga
1−x−y
N forming the gate insulating layer and GaN forming the buffer layer can be set to be equal to the difference in a-axis length between AlN (a=3.112 Å) and GaN (a=3.189 Å) or less. Then, a critical thickness with which crystal dislocation occurs increases, so that controllability for the threshold voltage is improved. The condition under which the difference in the a-axis length between In
x
Al
y
Ga
1−x−y
N and GaN becomes smaller than the difference in a-axis length between AlN and GaN is |a(x, y)−3.189|<3.189−3.112 Å. Hence,
|
y−
4.66
x|<
1  (4)
More preferably, the a-axis length of In
x
Al
y
Ga
1−x−y
N becomes equal to that of the GaN buffer layer. The condition for this is: a(x, y)=3.189 Å. Accordingly, y=4.66x can be obtained. Since crystal dislocation does not occur in this case, the thickness of the gate insulating layer can become arbitrary, so that controllability for the threshold voltage is improved greatly. More practically, assuming that an error within the range of −5% to +5% is allowed as a deviation of the ratio of mixed crystal from the lattice matching condition, this condition is expressed as:
|
y−
4.66
x|<
0.05  (5)
To make this gate insulating layer serve as a good gate insulating layer having a small leakage current, its band gap must be larger than that of In
z
Ga
1−z
N forming the channel layer. The band gap of In
x
Al
y
Ga
1−x−y
N is expressed as:
Eg
(
x, y
)=1.89
x+
6.2
y+
3.39(1−
x−y
)[eV]  (6)
Meanwhile, the band gap of In
z
Ga
1−z
N is expressed as:
Eg
(
z
)=1.89
z+
3.39(1−
z
)[eV]  (7)
Accordingly, the condition under which the band gap of In
x
Al
y
Ga
1−x−y
N becomes larger than that of In
z
Ga
1−z
N is Eg(x, y)>Eg(z). This yields the following inequality:
y>
0.533(
x−z
)  (8)
The object of the present invention can also be realized by using, as the gate insulating layer, a three-element type semiconductor superlattice such as In
T
Ga
1−T
N/Al
S
Ga
1−S
N, In
1−T
Ga
T
N/In
1−S
Al
S
N, In
T
Al
1−T
N/Al
1−S
Ga
S
N, or the like. In that case, the three-element type superlattice is equivalent to a four-element type semiconductor having an average composition weighted by the total thickness of each layer.
For example, an In
T
G

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