Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1999-12-30
2002-04-30
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S553000
Reexamination Certificate
active
06380800
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory circuits and to charge pumps used therein. More particularly this invention relates to the reduction of the capacitance area required for a charge pump through the use of passive or active filters at the pump output.
BACKGROUND OF THE INVENTION
Charge pumps are well known in the art as an on-chip voltage generator capable of providing a voltage more positive than the most positive external supply voltage and/or more negative than the most negative external supply voltage. The advantages of charge pumps are also well known in the art, such as providing a bias voltage for the substrate of an integrated circuit employing N-type and P-type wells, or for providing greater output voltage swings, among other advantages.
For purpose of simplification, the following discussion will focus on the charge pumps which must produce a positive voltage greater than the most positive supply voltage VCC; however, the concepts discussed are also applicable to charge pumps designed to produce a negative voltage greater than a negative supply voltage.
Most charge pumps comprise some variation of the basic charge pump
10
shown in the schematic diagram of FIG.
1
. The basic charge pump
10
configuration includes a ring oscillator
12
which provides a square wave or pulse train having voltage swings typically between ground and the most positive external power supply voltage, VCC. An invertor
14
, buffer amplifier, or Schmnitt trigger circuit may be used to sharpen the edges of the oscillating output signal of the ring oscillator
12
. A capacitor
16
is discharged into the load
24
through diode-connected transistor
20
. (Typically the drain and gate of the diode-connected transistor are coupled together to form the anode of a diode and the source forms the cathode of the diode.) Transistor
18
is coupled to the external power supply voltage, VCC, at terminal
22
. When the ring oscillator
12
produces a voltage close to ground, circuit node
26
is approximately at the voltage of the power supply minus a transistor threshold voltage, i.e. VCC-VT. When the ring oscillator
12
produces a voltage close to VCC, the incremental charge on capacitor
16
is delivered to the load
24
. Capacitor
16
is prevented from discharging to VCC by the reverse bias on diode-connected transistor
18
.
In the charge pump
10
, one pulse of current is delivered to the load
24
for every clock cycle of the ring oscillator. Therefore, the charge pump
10
has an active half-cycle in which current is delivered to the load
24
. However, charge pump
10
also has an inactive half-cycle in which capacitor
16
is precharged for the next active half-cycle. Although this inactive half-cycle is necessary to precharge the capacitor
16
, no current is delivered to the load
24
, which delays the attainment of the final desired voltage. Later advancements in charge pumps
10
have included injection of two current pulses into the load
24
for each cycle of the ring oscillator
12
, by utilizing both states of each ring oscillator cycle. This is known in the art as a two phased pump.
In most integrated electronic circuits, such as a memory chip, it is desirable that the final voltage at the load be reached as quickly as possible. Proper device functions and attributes, such as the integrity of stored data, cannot be guaranteed until the load has reached the proper value.
However, the rapid voltage ramping on the load does pose some problems such as increased pump stresses and/or breakdown on circuits near the pump's output caused from voltage peaks. This is particularly true as oxides become thinner and channel lengths are shortened. Too high a voltage can cause a breakdown in particular areas of advanced fabricated devices. One technique used to reduce the high voltage peak related stresses is to add more capacitance to the output of the pump. Even with added capacitance on the output of the pump, there are still significant peaks experienced by those active circuits which first receive the pump output. These peaks can lead to premature oxide wearout or CHC (channel hot carrier) effects. For an N-channel transistor, the channel hot carriers would be electrons. These electrons can experience large fields near the drain making them very energetic. These energetic electrons may get injected into the gate oxide resulting in shifted circuit characteristics.
Reducing the peak voltage stresses by adding more capacitance at the output of the pump also means adding more die area. Even if space or die area is available, such as under buss routings, this is typically not effective because much of the added capacitance would be distributed away from the charge pump output. Therefore, there is a need for reducing the voltage peak stresses seen by circuits near the pump's output without increasing the capacitance and associated die area.
SUMMARY OF THE INVENTION
The present invention provides a unique method and apparatus that can be fabricated on a semiconductor integrated circuit for efficiently reducing pump peak voltage stresses on circuits near the charge pump's output while reducing required capacitance and hence die area. An RC filter is added at the output of the charge pump which adds resistance to effectively reduce pump peak voltage stresses while lowering the amount of capacitance required to achieve a desired result as compared to a capacitance only solution. The added filter can be a one or more stage passive filter or an actively controlled filter.
Further, in accordance with the present invention, multiple filters can be respectively used for multiple charge pump loads.
These and other advantages and features of the invention will become more apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.
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patent: 5394320 (1995-02-01), Blodgett
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5404250 (1995-04-01), Hase et al.
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patent: 5656975 (1997-08-01), Imura
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patent: 5892407 (1999-04-01), Ishii
Dickstein , Shapiro, Morin & Oshinsky, LLP
Dinh Paul
Micro)n Technology, Inc.
Smith Matthew
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