Nonvolatile semiconductor memory having plural data storage...

Details Nonvolatile semiconductor memory having plural data storage... Nonvolatile semiconductor memory having plural data storage...

2000-09-22

2002-04-16

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185080, C365S185250

Reexamination Certificate

active

06373746

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from the prior Japanese Patent Applications No. 11-275327, filed Sep. 28, 1999; and No. 11-345299, filed Dec. 3, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and particularly relates to a nonvolatile semiconductor memory used as a Multi-level NAND cell type EEPROM, e.g., a four-level NAND cell type EEPROM.
There is known, as one of nonvolatile semiconductor memories, an NAND cell type EEPROM. This EEPROM has a memory cell array consisting of a plurality of NAND cell units. Each of the NAND cell units consists of a plurality of memory cells connected in series and two select transistors connected to both ends of the memory cells, respectively. The NAND cell unit is connected between a bit line and a source line.
Each memory cell consists of an n channel MOS transistor having a so-called stack gate structure in which a control gate electrode is stacked on a floating gate electrode. Each select transistor consists of an n channel MOS transistor having a structure in which an upper electrode is stacked on a lower electrode as in the case of the memory cell. It is the lower electrode, for example, that actually functions as the gate electrode of the select transistor.
One source region or one drain region is common to adjacent two transistors among a plurality of transistors (memory cells and select transistors) in an NAND cell unit.
Now, the concrete structure of an NAND cell type EEPROM will be described.
FIG. 1
shows part of a memory cell array of the NAND cell type EEPROM.
Each NAND cell unit consists of a plurality of (4, 8, 16 or the like) memory cells connected in series and two select transistors connected to both ends of the memory cells, respectively. The NAND cell unit is connected between bit lines BLi and source lines SL. Each of the source lines is connected to reference potential lines each formed of a conductive member such as polysilicon at preset positions.
The source lines SL extend in row direction, whereas the bit lines BLi and the reference potential lines extend in column direction. Contact portions on which the source line SL and the reference potential line contact are provided at intervals at which each source line SL intersects, for example, 64 bit lines, i.e., four bit lines BL
0
, . . . BL
63
. The reference potential lines is connected to so-called peripheral circuits provided on the peripheral section of the memory cell array.
Word lines (control gate lines) WL
1
, . . . and WLn extend in the row direction and the select gate lines SG
1
and SG
2
extend in the row direction, as well. The collection of the memory cells connected to one word line (control gate line) WLi is called one page. Further, the collection of the memory cells connected to the word lines WL
1
, . . . and WLn put between the two select gate lines SG
1
and SG
2
is called one NAND block or simply one block.
One page consist of, for example, 256-byte (256×8) memory cells. The memory cells in one page are programmed almost simultaneously. In addition, if one page consists of 256-byte memory cells and one NAND cell unit consists of eight memory cells, one block consists of 2048-byte (2048×8) memory cells. The memory cells in one page are erased almost simultaneously.
FIG. 2
is a plan view of one NAND cell unit in the memory cell array.
FIG. 3
is a cross-sectional view of the NAND cell taken along line III—III of
FIG. 2. 1

FIG. 4
is a cross-sectional view thereof taken along line IV—IV of FIG.
2
.
FIG. 5
shows an equivalent circuit of the devices of
FIGS. 2
to
4
.
In a p substrate (p-sub)
11
-
1
, a so-called double-well region, consisting of an n well region (Cell n-well)
11
-
2
and p well region (Cell p-well)
11
-
3
, is formed. The memory cells and select transistors are formed in the p well region
11
-
3
.
The memory cells and select transistors are arranged in an element region within the p well region
11
-
3
. The element region is surrounded by an element separation oxide film (element separation region)
12
formed on the p well region
11
-
3
.
In this example, one NAND cell unit consists of eight memory cells M
1
to M
8
connected in series and two select transistors S
1
and S
2
connected to the both ends of the memory cells, respectively.
Each memory cell consists of a silicon oxide film (gate insulating film)
13
formed on the p well region (Cell p-well)
11
-
3
, a floating gate electrode
14
(
14
1
,
14
2
. . .
14
8
) on the silicon oxide film
13
, a silicon oxide film (inter-polysilicon insulating film)
15
on the floating gate electrode
14
(
14
1
,
14
2
. . .
14
8
), a control gate electrode
16
(
16
1
,
16
2
. . .
16
8
) on the silicon oxide film
15
and a source-drain region
19
in the p well region (Cell p-well)
11
-
3
.
Each select transistor consists of a silicon oxide film (gate insulating film) formed on the p well region
11
-
3
, a gate electrode
14
(
14
9
,
14
10
) and
16
(
16
9
,
16
10
) on the silicon oxide film, and a source-drain region
19
in the p well region
11
-
3
.
The structure of the select transistor is similar to that of the memory cell for the following reason. By simultaneously forming the memory cells and the select transistors through the same process, the number of process steps is intended to be reduced to thereby reduce production cost.
One source region (n
+
diffused layer)
19
or one drain region (n
+
diffused layer)
19
is common to egg adjacent two transistors among the plural transistors (memory cells and select transistors) in the NAND cell unit.
The memory cells and the select transistors are covered with a silicon oxide film (CVD oxide film)
17
formed by the CVD method. A bit line
18
connected to one end of the NAND cell unit (n
+
diffused layer
19
) is arranged on the CVD oxide film
17
.
FIG. 6
shows the well structure of the NAND cell type EEPROM.
In the p substrate (p-sub)
11
-
1
, a so-called double-well region, consisting of the n well region (Cell n-well)
11
-
2
and the p well region (Cell p-well)
11
-
3
, an n well region (n-well)
11
-
4
and a p well region (p-well)
11
-
5
.
The double-well region is formed on a memory cell array section, and the n well region
11
-
4
and the p well region
11
-
5
are formed on a peripheral circuit section.
The memory cells are formed in the p well region
11
-
3
. The n well region
11
-
2
and the p well region
11
-
3
are set to have the same potential.
A high voltage n channel MOS transistor applied with a higher voltage than a power supply potential is formed on the p substrate (p-sub)
11
-
1
. A low voltage p channel MOS transistor applied with the power supply voltage is formed on the n well region (n-well)
11
-
4
and a low voltage n channel MOS transistor applied with the power supply voltage is formed on the p well region (p-well)
11
-
5
.
Next, the basic operation of the NAND cell type EEPROM will be described.
First, to facilitate the description, the following preconditions are specified. Two level data “0” and “1” are stored in a memory cell; a state in which the threshold voltage of the memory cell is low (e.g., the threshold voltage is negative) is a “0” state; and a state in which the threshold voltage of the memory cell is high (e.g., the threshold voltage is positive) is a “1” state.
In an ordinary two-level NAND cell type EEPROM, a state in which the threshold voltage of the memory cell is low is set at a “1” state and that in which the threshold voltage is high is set at a “0” state. However, as will be described later, the present invention is mainly intended for a multi-level (e.g., four-level) NAND type EEPROM. Considering this, it is assumed that a state in which the threshold voltage of the memory cell is low is a “0” state and that in which the threshold voltage of the memory cell is high is a “1” state.
As for the memory cell, it is assumed

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