Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-08-27
2002-05-07
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S760000, C257S324000, C257S354000, C257S513000, C257S669000, C257S700000, C257S691000, C257S903000, C438S624000, C438S641000, C438S643000, C438S257000, C438S435000, C438S427000, C438S424000, C438S668000
Reexamination Certificate
active
06384466
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed, generally, to an assembly having a multi-layer dielectric and its method of manufacture.
2. Description of the Prior Art
Dielectric layers are very important in the production of integrated circuits because they provide an insulating barrier between conductive layers and protect the underlying layers from such things as impurities, moisture, and stress related impacts. It is desirable that the dielectric layer fill the spaces between the parallel conductors. Otherwise, voids left between the conductors can cause the circuit to fail for a variety of reasons, such as latent defects caused by impurities and moisture. Voids between the parallel conductors can also cause the circuits to fail due to electric shorts between structures formed subsequent to the dielectric deposition. Furthermore, certain dielectric characteristics cause undesirable effects, such as “cross talk” between parallel conductors of current. Accordingly, the quality of the dielectric layer is a factor in the reliability and performance of the integrated circuit.
FIG. 9
illustrates a dielectric formation problem known in the art known as “shadowing”, wherein some areas in the openings
118
between the structures
112
are more prone to developing voids
110
during the formation of the dielectric layer
102
, thereby resulting in a less effective integrated circuit. Various attempts have been made to reduce or eliminate shadowing, and thereby improve the overall quality of the dielectric layer.
It is known to form multiple dielectric layers to provide benefits not available with a single dielectric layer to improve dielectric quality. However, several deficiencies exist in the prior art. For example, it is known to form a multi-layer dielectric having an adhesive coating between each dielectric layer. The adhesive coating, however, introduces an additional step in the fabrication process, which reduces manufacturing efficiency and increases costs. Also, it is known to form three layers of dielectric material having varying degrees of quality and thickness, with the third top layer being relatively thick. Formation of a three layered dielectric, however, requires significant manufacturing time and cost, particularly when thickness and high quality are necessary characteristics of one of the layers.
Accordingly, the need exists for an improved multiple layer dielectric providing good gap-fill characteristics, whereby only two layers are needed, and an adhesive layer is not needed.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to an assembly having a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over the first dielectric layer. Reducing the aspect ratio of the opening by forming the first dielectric layer and completing the dielectric layer by forming the second dielectric layer may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and spacing between the shower head and the assembly.
The present invention also includes a method of forming a dielectric layer in an opening having an aspect ratio of greater than about two comprising forming a first dielectric layer in the opening wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than two, and forming a second dielectric layer over the first dielectric layer.
The present invention also may be embodied in and used to form dielectrics associated with structures such as electrical conductors in integrated circuits, such as are used to form memory arrays, logic circuits, memory devices, processors, and systems.
The present invention solves problems experienced with the prior art because it combines both quality and efficiency in the forming process. The present invention provides a dielectric layer and method of manufacture comprising a first layer dielectric having improved gap-fill at a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.
Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.
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Kirkpatrick & Lockhart LLP
Meier Stephen D.
Micro)n Technology, Inc.
Mitchell James
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