Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-19
2002-07-30
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S758010, C324S765010
Reexamination Certificate
active
06426639
ABSTRACT:
TECHNICAL FIELD
The present invention is directed toward a method and apparatus for capacitively applying a test signal to a semiconductor die.
BACKGROUND OF THE INVENTION
Semiconductor dies form the core of semiconductor modules and other devices which are used extensively throughout the computer industry, telecommunication industry, and myriad related industries. The dies are typically tested during the manufacturing process to ensure that the dies conform to operational specifications. The resulting dies are then installed in the semiconductor module or device.
Semiconductor dies are typically tested by placing conductive test leads in contact with respective bond pads of the die, applying a test signal to the bond pads via the test leads, and determining whether the die responds with the proper output signals. To ensure proper transmission of the test signals to the die, the test leads may be placed in physical contact with the bond pads of the die using a variety of methods. One method is to solder the leads to the bond pads. Another method is to couple the leads to terminals and then force the terminals into engagement with the bond pad, deforming both the terminals and the bond pad. One drawback of the foregoing methods is that they include at least temporarily connecting the leads or terminals to the bond pads prior to testing and then disconnecting the leads or terminals subsequent to testing. Connecting and disconnecting the leads is time consuming and may damage the bond pads, making it difficult to permanently install the die in a semiconductor module when testing has been completed.
One approach to solving the foregoing problem has been to replace the test leads with test pads, which are capacitively coupled to corresponding bond pads of the die. The capacitive coupling is formed by a dielectric layer positioned between an electrically conductive portion of the test pad and the corresponding conductive portion of the bond pad. No direct physical contact is required between the conductive portions of the test pads and the corresponding bond pads. As a result, the likelihood that the bond pads will become damaged by the test pads is reduced. This method may also be less expensive than conductive testing methods because capacitively coupling and decoupling the bond pads and test pads may require less time and effort than conductively connecting and disconnecting the bond pads and test leads.
Conventional methods for capacitively testing a semiconductor die suffer from several drawbacks. The capacitive test pads of a device used to test the die may be large compared to bond pads and may not be aligned with the bond pads. As a result, an interlayer must be placed between the bond pads of the die and the capacitive test pads. Contacts on the surface of the interlayer are aligned with the capacitive test pads of the test device and are connected through the interlayer to the bond pads of the die. Forming the interlayer requires an additional manufacturing step and it may be necessary to remove the interlayer before the die may be permanently installed, requiring yet another manufacturing step.
Another drawback with a conventional method and device used to capacitively test semiconductor dies is that the device has a thermal expansion coefficient which is different than the thermal expansion coefficient of the die material. As a result, when the die is tested at high temperatures, the die and the test device expand at different rates and capacitive coupling may not be maintained between the die and the test apparatus.
Yet another draw back with conventional testing devices is that the capacitive test pads may be flush with the surface of the test device. When the test device is placed adjacent the die for testing, dust particles or other contaminants may become trapped between the test device and the die, damaging the die. Still another drawback of conventional testing methods is that they may require that a liquid or gel dielectric material be placed on the bond pads of the die prior to testing. The liquid or gel dielectric material may be difficult to remove after testing, contaminating the die and inhibiting good connections between the bond pads of the die and lead wires which are connected to the bond pads when the die is permanently installed.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for capacitively testing a semiconductor die or wafer having first and second die terminals. In one embodiment, the apparatus comprises a substrate positionable proximate the die and having a coefficient of thermal expansion approximately equal to a thermal expansion coefficient of the die. The apparatus further comprises first and second test terminals positioned on a surface of the substrate. The first test terminal has a conductive portion aligned with and spaced apart from a conductive portion of the first die terminal. The first test terminal may accordingly be capacitively coupled to the first test terminal when the substrate is positioned proximate to the die. The second test terminal is aligned with the second die terminal when the conductive portion of the first test terminal is aligned with the first die terminal.
In one embodiment of the invention, the apparatus further comprises a dielectric material positioned intermediate the conductive portion of the first test terminal and the conductive portion of the first die terminal. The dielectric material is attached to the conductive portion of the first test terminal in one embodiment and is attached to the first die terminal in another embodiment. In yet another embodiment, the die is one of a plurality of dies comprising a silicon wafer and the substrate is sized and shaped to be positioned adjacent the silicon wafer.
The invention is also directed toward a method for manufacturing an apparatus for capacitively testing a semiconductor die having first and second die terminals, each connector having a conductive surface. The method comprises forming a first test terminal on a substrate such that the first test terminal has a conductive surface aligned with and spaced apart from the conductive surface of the first die terminal. The method further comprises forming a second test terminal on the substrate having a conductive portion aligned with the second die terminal while the first test terminal is aligned with the first die terminal. The method further comprises positioning a dielectric material intermediate at least the conductive portion of the first test terminal and the conductive surface of the first die terminal when the first test terminal is aligned with the first die terminal.
In one embodiment, a method for manufacturing an apparatus in accordance with the invention further comprises applying a layer of photoresist material to a surface of the substrate, exposing a first region of the photoresist material to a selected radiation to form an exposed region of photoresist material, and shielding a second region of the photoresist material from exposure to the selected radiation to form a shielded region of photoresist material. The method further comprises removing one of the exposed and shielded regions, and removing substrate material previously covered by the other of the exposed and shielded regions to form a projection which is aligned with the first die terminal when the substrate is positioned proximate the die.
In yet another embodiment of a method in accordance with the invention, the first test terminal is formed by applying an insulating layer to a surface of the substrate and forming a first portion of conductive material on the insulating layer, the first portion of conductive material being aligned with the first die terminal when the substrate is positioned proximate to the die. The method further comprises forming a second portion of conductive material on the insulating layer aligned with the second die terminal when the first portion of conductive material is aligned with the first die terminal.
REFERENCES:
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5177439 (1
Akram Salman
Farnworth Warren M.
Dorsey & Whitney LLP
Sherry Michael
Tang Minh N.
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