Digital-to-analog converter with high dynamic range

Details Digital-to-analog converter with high dynamic range Digital-to-analog converter with high dynamic range

2000-10-02

2002-04-09

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000, C455S450000

Reexamination Certificate

active

06369735

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital-to-analog converters, and more specifically relates to a digital-to-analog converter which has high dynamic range.
BACKGROUND OF THE INVENTION
Code-Division Multiple Access (CDMA) is a digital cellular technology that uses spread-spectrum techniques. Unlike competing systems, such as Global System for Mobile Communications (GSM), that use time-division multiplexing (TDM), CDMA does not assign a specific frequency to each user. Instead, every channel uses the full available spectrum. Individual conversations are encoded with a pseudo-random digital sequence.
CDMA started out as a military technology, first used during World War II by the English allies to foil German attempts at jamming transmissions. The allies decided to transmit over several frequencies, instead of one, making it difficult for the Germans to pick up the complete signal.
In third generation CDMA, the transmit signal waveform is continuous in the reverse link. As a result, the signal power is varied with the data rate. The variation is on a frame basis (i.e., 80/40/20/5 milliseconds in an IS-2000 CDMA wireless communication system) and might be changed by, for example, more than 20 dB for a 1×IS-2000 system and even higher for a 3×+IS-2000 system. This extra dynamic range imposes a tighter requirement for the transmit digital-to-analog converter. This requirement translates directly to, for example, an extra 3 to 4 bits for 1×CDMA.
One approach at solving the problem is to increase the number of bits for the digital-to-analog converter. This might, for example, require a 12-14 bit digital-to-analog converter for a 1×CDMA system and over 14 bits for a 3×+CDMA system. However, it is advantageous to avoid increasing the number of bits for a digital-to-analog converter because doing so complicates the implementation and substantially increases the power consumption, die size, cost, etc.
OBJECTS AND SUMMARY
It is an object of an embodiment of the present invention to provide a digital-to-analog converter which has high dynamic range.
Another object of an embodiment of the present invention is to increase the dynamic range of a digital-to-analog converter without increasing the number of bits.
Still another object of an embodiment of the present invention is to provide a digital-to-analog converter which is configured to digitally scale the signal level before the digital-to-analog conversion, and then scale it back in the analog stage of the converter.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a device that is configured to implement a novel scaling scheme wherein a signal level is digitally scaled before a digital-to-analog converter, and is scaled back in the analog stage of the digital-to-analog converter. The scaling normalizes the input mean power to the digital-to-analog converter. Therefore, the digital-to-analog converter has a generally constant power and no extra dynamic range is needed.
Preferably, the device which is configured to provide the scaling scheme is configured to receive fundamental, dedicated, supplemental and pilot channels, and is configured to combine the four channels to form a single signal. The single signal is then received by a gain scaler, a shaping filter, a digital-to-analog converter, and an analog filter of the device. Specifically, the gain scaler receives the signal, and applies a first gain thereto. The shaping filter then receives the signal, and the signal then travels to the digital-to-analog converter wherein a second gain is applied to the signal. Preferably, the second gain is inversely proportional to the first gain, thereby providing that the signal level is digitally scaled before the digital-to-analog converter and is scaled back in the analog stage of the digital-to-analog converter. The signal then preferably travels to the analog filter. The device is configured such that a digital signal processor (DSP) communicates with the gain scaler to control the first gain and communicates with the digital-to-analog converter to control the second gain.


REFERENCES:
patent: 5196850 (1993-03-01), Duffy et al.
patent: 6167273 (2000-12-01), Mandyam
patent: 6271782 (2001-08-01), Steensgaard-Madsen
patent: 6292122 (2001-09-01), Younis et al.

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