Digital phase locked loop circuit

Details Digital phase locked loop circuit Digital phase locked loop circuit

2000-04-28

2002-05-07

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000, C331S017000

Reexamination Certificate

active

06384650

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a digital phase locked loop (PLL) circuit, in particular, which has a plurality of loop circuits.
DESCRIPTION OF THE RELATED ART
FIG. 1
is a block diagram showing a structure of a conventional digital PLL circuit. The conventional digital PLL circuit consists of a frequency divider
1
which divides a frequency of an output signal, an adder
2
which subtracts the output signal whose frequency is divided at the frequency divider
1
from an inputted signal and outputs the subtracted signal as a stationary phase difference, a constant multiplier
3
which multiplies the stationary phase difference outputted from the adder
2
by a constant K
1
, a constant multiplier
13
which multiplies the stationary phase difference multiplied the constant K
1
at the constant multiplier
3
by a constant K
2
, an integrator
4
which integrates the stationary phase differences multiplied the constant K
2
at the constant multiplier
13
, an adder
42
which adds the stationary phase difference multiplied the constant K
1
at the constant multiplier
3
and the stationary phase differences integrated at the integrator
4
and outputs the added result, a digital to analog converter (DAC)
5
which converts a digital signal outputted from the adder
42
to an analog signal, and a voltage controlled oscillator (VCO)
6
which outputs a signal having a frequency based on the analog signal converted at the DAC
5
, and a frequency of the output signal outputted from the VCO
6
is divided at the frequency divider
1
. In this structure, a first loop circuit is composed of the frequency divider
1
, the adder
2
, the constant multiplier
3
, the adder
42
, the DAC
5
, and the VCO
6
, and a second loop circuit is composed of the frequency divider
1
, the adder
2
, the constant multiplier
3
, the constant multiplier
13
, the integrator
4
, the adder
42
, the DAC
5
, and the VCO
6
.
Next, an operation of this conventional digital PLL circuit is explained. First, a frequency of a signal outputted from the VCO
6
is divided into 1/N at the frequency divider
1
and the signal whose frequency is divided is inputted to the adder
2
.
At the adder
2
, the signal whose frequency is divided at the frequency divider
1
is subtracted from an inputted signal and the subtracted result is outputted as a stationary phase difference. That is, a phase difference corresponding to the difference between a frequency of the inputted signal and a free-running frequency of the VCO
6
is outputted from the adder
2
as the stationary phase difference.
At the constant multiplier
3
, the stationary phase difference outputted from the adder
2
is multiplied by a constant K
1
and the stationary phase difference multiplied by the constant K
1
is outputted to the constant multiplier
13
and the adder
42
.
At the constant multiplier
13
, the stationary phase difference multiplied the constant K
1
at the constant multiplier
3
is multiplied by a constant K
2
and the stationary phase difference multiplied the constant K
2
is outputted to the integrator
4
.
At the integrator
4
, the stationary phase differences multiplied the constant K
2
at the constant multiplier
13
are integrated.
At the adder
42
, the stationary phase difference multiplied the constant K
1
at the constant multiplier
3
and the stationary phase differences integrated at the integrator
4
are added and the added result is outputted.
The digital signal outputted from the adder
42
is inputted to the DAC
5
, and the digital signal inputted to the DAC
5
is converted to an analog signal, and the converted analog signal is outputted to the VCO
6
.
At the VCO
6
, a signal having a frequency based on the signal outputted from the DAC
5
is outputted as an output signal.
By a series of the feedback operation mentioned above, when a phase difference corresponding to the difference between a frequency of the inputted signal and a free-running frequency of the VCO
6
, that is, the stationary phase difference outputted from the adder
2
becomes equal to the stationary phase difference outputted from the adder
2
at the previous feedback operation, the frequency is pulled in to the loop circuits and the phase is locked.
At transmitting equipment, especially at a synchronous multiplexer used a structure called a synchronous digital hierarchy (SDH), in case that a clock source to be synchronized is lost, it is required that a synchronizing clock frequency is memorized and the synchronizing clock frequency is held for a long period of time. This function is called a hold-over function.
In this conventional example, when the clock source to be synchronized is lost, the output from the constant multiplier
3
is forced to be zero. With this, the both first and second loop circuits are cut, and the difference between the frequencies of the inputted signals integrated at the integrator
4
and the free-running frequency of the VCO
6
is made to be a constant, and by using the difference made to be a constant, the frequency of the signal outputted from the VCO
6
via the adder
42
and the DAC
5
is controlled to be a constant, and the hold-over function is realized.
However, in case that the clock source to be synchronized is lost and the hold-over function mentioned above is made to work, the analog voltage outputting from the DAC
5
and the free-running frequency of the VCO
6
are largely changed by the change of power supply voltage or ambient temperature. Therefore, in order that the function of hold-over is made to be a stable operation for a long period of time, the change of the power supply voltage or the ambient temperature must be made to be as small as possible, and there is a problem that the cost to solve the matter becomes large.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a digital phase locked loop (PLL) circuit that can realize a high accurate function of hold-over even when power supply voltage fluctuates and ambient temperature changes.
According to a first aspect of the present invention for achieving the object mentioned above, at a digital PLL circuit, which provides a first and a second loop circuits that make an inputted frequency and an output frequency equivalent by a feedback operation of the phase of said output frequency, and in which in case that a clock source to be synchronized is lost, a clock frequency being synchronized is memorized and held for a long period of time, the digital PLL circuit provides a third loop circuit which compares said output frequency with a predetermined constant frequency and uses the compared result for the feedback operation at said first and second loop circuits.
According to a second aspect of the present invention in the first aspect, said third loop circuit provides a fixed frequency oscillator which outputs a signal having a predetermined constant frequency, a calculating means for calculating a difference between said frequency of said signal outputted from said fixed frequency oscillator and said output frequency, a memorizing means for memorizing said difference calculated at said calculating means, a comparing means for comparing a difference between said frequency of said signal outputted from said fixed frequency oscillator and a current output frequency with said difference memorized in said memorizing means, and a voltage controlled oscillator (VCO) which outputs a signal having a frequency based on the compared result at said comparing means. And control is performed so that said difference between said frequency of said signal outputted from said fixed frequency oscillator and said current output frequency, and said difference memorized in said memorizing means are made to be equal.
According to a third aspect of the present invention in the second aspect, said calculating means, to which a signal that the frequency of said signal outputted from said fixed frequency oscillator is divided and a signal that the frequency of said output frequency is divid

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