Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-03-23
2002-05-07
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S745000
Reexamination Certificate
active
06383933
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of integrated circuit structures and, in particular, to a planarization process that uses organic material to enhance shallow trench isolation (STI) planarization, or other planarization processes, in integrated circuit manufacturing by preventing oxide dishing during chemical mechanical polishing (CMP).
2. Description of Related Art
The advancement in complexity of integrated circuit structures has led to the requirement of more layers formed on the silicon substrate surface. The additional layers result in an uneven topography. The uneven topography affects lithographic depth of focus, which negatively impacts the resolution of small image sizes in the photolithographic techniques used in manufacturing integrated circuits.
Planarization processes are used to planarize, or flatten, the topography of the substrate surface. Chemical mechanical polishing (CMP) is a planarization technique that is used to create a flat surface. However, CMP planarization results in oxide dishing in large areas between fine features. Oxide dishing is a problem because it has a negative impact on electrical isolation, etch uniformity in subsequent processing, and pattern definition.
Oxide dishing occurs when local portions of the surface of the structure are polished too much during the CMP step, resulting in depressed areas in the surface. In CMP, a rotating polishing pad polishes the surface of the structure to remove the excess oxide. The areas between features, especially wide features, are prone to oxide dishing because the larger depressed areas are also polished by the rotating polishing pad.
FIG. 1
illustrates the problem of oxide dishing in a structure having uneven topography after CMP planarization.
Shallow trench isolation (STI) is a technique for isolating active devices in high density integrated circuits. Integrated circuit manufacturers have, until recently, avoided STI because STI, when compared with other device isolation processes, is complex. STI requires more process control than the commonly used local oxidation of silicon (LOCOS) isolation. However, with the increasing need for higher device density, STI is becoming more widely utilized since it encroaches less in the active area of the device.
One difficulty in implementing STI has been that, without reactive ion etching (RIE) etch back processing, CMP planarization has been unable to adequately planarize the substrate surface due to the large feature density variations on the device surface which leads to the above-described oxide dishing problem. In the past, RIE etch back was used to generate artificial topography in oxide to form features on the wafer. The RIE etch back adds to the complexity of the STI process because it requires an additional photolithography step to form a resist block as well as the RIE etch back step.
Slurry manufacturers have been trying to eliminate the need for RIE etch back processing by looking for materials that improve the typical 5:1 removal rate selectivity of oxide to nitride to values greater than 20:1 to solve the oxide dishing problem. However, an ideal slurry has not yet been discovered.
SUMMARY OF THE INVENTION
The present invention provides a planarization process that is enhanced by an organic material having a high CMP selectivity to silicon dioxide. The high CMP selectivity of the organic material prevents the oxide dishing which normally occurs during chemical mechanical polishing.
In accordance with the invention, silicon dioxide is formed over a structure having uneven topography. A thin layer of organic material is then formed over the silicon dioxide. A patterned masking material is then formed over the organic material and the exposed portions of the organic material are etched, stopping on the oxide. The masking material is patterned such that it masks the areas prone to oxide dishing, thereby leaving the organic material in those areas.
The masking material is then stripped away, leaving exposed surfaces of the organic material and of silicon dioxide. The structure is then polished, utilizing CMP, to planarize the surface. The organic material may then be removed with a highly selective oxygen plasma or is left on the wafer surface as part of the dielectric. Given the thinness of the layer of the organic material, the surface of the structure is still substantially planarized after removal of the organic material. The organic material, being non-etchable by CMP and its high selectivity to silicon dioxide, stops the etching during the polishing step and thereby prevents oxide dishing.
The organic material stops the etching because organics have high selectivity to silicon dioxide because it appears that the organic material cannot be chemically damaged and mechanically removed by the slurry. It appears that organics have almost infinite selectivity to silicon dioxide in silicon dioxide polish slurries. This high selectivity prevents the organic material from being polished by the slurries.
The organic material eliminates the oxide dishing problem that generally occurs during the CMP step in STI planarization. In multilevel metalization processes, the organic material solves the dishing problem as well in large open areas greater than 20 &mgr;m between metal features.
REFERENCES:
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5961794 (1999-10-01), Morita
patent: 6251788 (2001-06-01), Liou
Sethna Prochy
Shu Jen
Thomas Michael E.
National Semiconductor Corporation
Powell William A.
Stallman & Pollock LLP
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