Multiple phase voltage regulator system

Details Multiple phase voltage regulator system Multiple phase voltage regulator system

2000-06-30

2002-09-10

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S283000, C324S076590

Reexamination Certificate

active

06448746

ABSTRACT:

BACKGROUND
The invention generally relates to a multiple phase voltage regulator system.
A DC-to-DC voltage regulator typically is used to convert a DC input voltage to either a higher or a lower DC output voltage. One type of voltage regulator is a switching regulator that is often chosen due to its small size and efficiency. The switching regulator typically includes one or more switches that are rapidly opened and closed to transfer energy between an inductor (a stand-alone inductor or a transformer, as examples) and an input voltage source in a manner that regulates an output voltage.
As an example, referring to
FIG. 1
, one type of switching regulator is a Buck switching regulator
10
that receives an input DC voltage (called V
IN
) and converts the V
IN
voltage to a lower regulated output voltage (called V
OUT
) that appears at an output terminal
11
. To accomplish this, the regulator
10
includes switches
20
and
21
(a combination of a metal-oxide-semiconductor field-effect-transistor (MOSFET) and a passive diode or twin MOSFETs, for example). Switch
20
is operated (via a voltage called V
SW
) in a manner to regulate the V
OUT
voltage, as described below.
Referring also
FIGS. 2 and 3
, in particular, the switch
20
opens and closes to control energization/de-energization cycles
19
(each having a constant duration called T
S
) of an inductor
14
. In each cycle
19
, the regulator
10
asserts, or drives high, the V
SW
voltage during an on interval (called T
ON
) to close the switch
20
and transfer energy from an input voltage source
9
to the inductor
14
. During the T
ON
interval, a current (called I
L
) of the inductor
14
has a positive slope. During an off interval (called T
OFF
) of the cycle
19
, the regulator
10
deasserts, or drives low, the V
SW
voltage to open the switch
20
and isolate the input voltage source
9
from the inductor
14
. At this point, the level of the I
L
current is not abruptly halted, but rather, the switch
21
begins conducting to transfer energy from the inductor
14
to a bulk capacitor
16
and a load (not shown) that are coupled to the output terminal
11
. The bulk capacitor
16
serves as a stored energy source that is depleted by the load, and additional energy is transferred from the inductor
14
to the bulk capacitor
16
during each T
ON
interval.
For the Buck switching regulator, the ratio of the T
ON
interval to the total switching period, T
S
(summation of T
ON
+T
OFF
), called a duty cycle, generally governs the ratio of the V
OUT
to the V
IN
voltages. Thus, to increase the V
OUT
voltage, the duty cycle may be increased, and to decrease the V
OUT
voltage, the duty cycle may be decreased.
As an example, the regulator
10
may include a controller
15
(see
FIG. 1
) that regulates the V
OUT
voltage by using a pulse width modulation (PWM) technique to control the duty cycle. In this manner, the controller
15
may include an error amplifier
23
that amplifies the difference between a reference voltage (called V
REF
) and a voltage (called V
P
(see FIG.
1
)) that is proportional to the V
OUT
voltage. Referring also to
FIG. 5
, the controller
15
may include a comparator
26
that compares the resultant amplified voltage (called V
C
) with a sawtooth voltage (called V
SAW
) and provides the V
SW
signal that indicates the result of the comparison. The V
SAW
voltage is provided by a sawtooth oscillator
25
and has a constant frequency (i.e., 1/T
S
).
Due to the above-described arrangement, when the V
OUT
voltage increases, the V
C
voltage decreases and causes the duty cycle to decrease to counteract the increase in V
OUT
. Conversely, when the V
OUT
voltage decreases, the V
C
voltage increases and causes the duty cycle to increase to counteract the decrease in V
OUT
.
The voltage regulator may be made in the form of a voltage regulator module (VRM), a semiconductor package, or chip, that may be inserted into a corresponding connector slot, for example. More particularly, multiple VRMs, such as the VRMs
37
and
38
that are depicted in
FIG. 6
, may be coupled in parallel to form a multiple phase voltage regulator system
36
. In this manner, referring also
FIGS. 7 and 8
, energization/de-energization cycles
40
a
(depicted by an internal switching voltage of the VRM
37
called V
SW1
) of the VRM
37
is interleaved with respect to the energization cycles
40
b
(depicted by an internal switching voltage of the VRM
38
called V
SW2
) of the VRM
38
. As depicted in
FIGS. 7 and 8
, the effective switching period (called T
S1
) of the system
36
is one half as long as the switching period (called T
S2
) of either VRM
37
or
38
. Thus, the system
36
operates at twice the switching frequency of the VRM
37
,
38
, an operation that provides better transient response performance than either VRM
37
,
38
may provide by itself. More than two VRMs (three or four, for example) may be coupled together in parallel and interleaved accordingly to further increase the overall switching frequency of the system
36
.
For purposes of ensuring that each VRM
37
,
38
operates in the appropriate time slot, the energization/de-energization cycles of VRMs
37
and
38
may be controlled by synchronization signals to regulate the phasing of the system
36
. In this manner, the VRM
37
may receive a SYNC
1
signal that is depicted in
FIG. 9
, and the VRM
38
may receive a SYNC
2
signal that is depicted in FIG.
10
. The SYNC
1
signal includes pulses
42
a
, each of which enables a particular energization/de-energization cycle of the VRM
37
. The pulses
42
a
are interleaved with pulses
42
b
of the SYNC
2
signal. Each pulse
42
b
of the SYNC
2
signal enables a particular energization/de-energization cycle of the VRM
38
.
A system of interleaved VRMs (such as the system
36
, for example) may supply power to a computer system. In this manner, a motherboard may include several slots, or connectors, to receive VRMs. For purposes of providing flexibility in the number of VRMs that are used and thus, the number of phases of the system, the connectors typically appear in an ordered sequence on the motherboard. This sequence defines the placement of the VRMs to form a particular multiple phase system. If the VRMs are not inserted into the appropriate slots, then the appropriate synchronization signals may not be furnished to the slots, and thus, the power supply system may not function properly.
For example, a particular motherboard may have four VRM slots: Slot
1
, Slot
2
, Slot
3
and Slot
4
. To establish a two phase voltage regulator system, an ordering scheme that is imposed by the motherboard may require that the two VRMs are inserted in Slot
1
and Slot
2
, as Slot
1
and Slot
2
receive the synchronization signals to implement a two phase interleaved switching regulator system. Thus, if the VRMs are inserted into Slot
1
and Slot
3
, for example, the voltage regulator system may not function properly. Therefore, such an arrangement does not allow flexibility in the insertion and use of the VRMs.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.


REFERENCES:
patent: 4137565 (1979-01-01), Mager et al.
patent: 5390068 (1995-02-01), Schultz et al.
patent: 5638264 (1997-06-01), Hayashi, et al.
patent: 5929618 (1999-07-01), Boylan, et al.
patent: 6031743 (2000-02-01), Carpenter et al.
patent: 6052790 (2000-04-01), Brown
patent: WO 96/24234 (1996-08-01), None
patent: WO 00/33153 (2000-06-01), None

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