Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-12-01
2002-06-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S381000, C438S382000, C438S383000, C438S384000
Reexamination Certificate
active
06399456
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a resistor and a capacitor electrode in an integrated circuit.
2. Description of Related Art
An integrated circuit includes various kinds of circuit components, such as bi-polar junction transistors (BJT), metal-oxide semiconductor (MOS) transistors, junction diodes, resistors, and capacitors, that are arranged in a particular manner to provide the desired functionality.
FIGS. 1A-1F
are schematic, cross-sectional diagrams used to depict the steps involved in a conventional method for fabricating a resistor and a capacitor electrode in an integrated circuit. The resistor is to be connected to a MOS transistor, while the capacitor electrode is to be used as a bottom electrode for a capacitor connected to the MOS transistor.
Referring first to
FIG. 1A
, in the initial step, a semiconductor substrate
10
is prepared. The substrate
10
is formed with a P-well
16
and an N-well
18
. Isolation structures
14
are formed at predefined locations over the substrate
10
to define a plurality of active regions
12
. Furthermore, a layer of silicon nitride
20
is formed over each of the active regions
12
.
Referring next to
FIG. 1B
, in the subsequent step, the silicon nitride layer
20
over each of the active regions
12
is removed through a wet-etching process. After this, a sacrificial oxide layer
22
is formed over the entire top surface of the wafer to a thickness of about 300 Å (angstrom). Subsequently, an ion-implantation process is performed to dope ionized boron difluoride at an energy of about 60 KeV (kiloelectronvolt) with a concentration of about 3.4×10
12
ions/cm
2
into the channel regions in the substrate
10
. After this, an N-channel for depletion mode N-channel MOS (NMOS) is formed in the P-well
16
by performing an ion-implantation process to dope ionized phosphorous at an energy of about 60 KeV with a concentration of about 1.7×10
13
ions/cm
2
into the P-well
16
.
Referring next to
FIG. 1C
, in the subsequent step, a photoresist layer
23
is coated over the wafer in such a manner as to mask the N-well
18
while unmasking the P-well
16
. Then, with the photoresist layer
23
serving as mask, an ion-implantation process is performed on the wafer to dope ionized boron at an energy of 70 KeV with a concentration of 1.5×10
12
ions/cm
2
into the unmasked P-well
16
. After this, the ion-implantation process is performed again to dope ionized boron at a higher energy of 180 KeV with a higher concentration of 8×10
12
ions/cm
2
into the unmasked P-well
16
. Through these two ion-implantation processes, the P-well
16
is converted into a retrograde P-well in which the impurity concentration decreases with height. This gives the retrograde P-well
16
a high anti-punchthrough capability. After this, the entire photoresist layer
23
is removed.
Referring next to
FIG. 1D
, in the subsequent step, a polysilicon layer
24
is formed over the sacrificial oxide layer
22
through a chemical-vapor deposition (CVD) process to a thickness of about 2,000 Å. Next, an ion-implantation process is performed to dope ionized phosphorous at an energy of about 50 KeV with a concentration of about 6×10
15
ions/cm
2
into the polysilicon layer
24
.
Referring next to
FIG. 1E
, in the subsequent step, a photoresist layer
25
is coated over the wafer in such a manner as to mask the part of the polysilicon layer
24
(
FIG. 1D
) that lies directly above the P-well
16
and is to be formed by definition into a lightly-doped polysilicon region, as indicated by the reference numeral
28
, while unmasking the part of the polysilicon layer
24
that is laid directly above the N-well
18
and is to be formed by definition into a heavily-doped polysilicon region, as indicated by the reference numeral
26
. Then, with the photoresist layer
25
serving as mask, an ion-implantation process is performed to dope ionized phosphorous at an energy of about 50 KeV with a concentration of about 1.5×10
16
ions/cm
2
into the unmasked part of the polysilicon layer
24
. After this, the entire photoresist layer
25
is removed. Subsequently, an annealing process is performed on the polysilicon layer
24
at a temperature of about 850° C. in a gaseous environment of argon or nitrogen.
Referring next to
FIG. 1F
, in the subsequent step, the entire polysilicon layer
24
(
FIG. 1D
) is selectively removed through a photolithographic and etching process. The remaining part of the lightly-doped part
28
of the polysilicon layer
24
over the isolation structure
14
in the P-well
16
serves as a resistor for the integrated circuit, whereas the remaining part of the heavily-doped part
26
of the polysilicon layer
24
over the isolation structure
14
in the N-well
18
serves as a bottom electrode for a capacitor (not shown) that is to be subsequently formed in the integrated circuit.
The foregoing method for fabricating the resistor and the capacitor electrode, however, has the following drawbacks.
First, since the photoresist layer
25
is used as mask in the high-concentration ion implantation, the subsequent removal of the entire photoresist layer
25
and the selected part of the polysilicon layer
24
may be incomplete.
Second, during the ion implantation on the polysilicon layer
24
, the polysilicon layer
24
can be easily contaminated by the particles and metals from the implantation machine since the polysilicon layer
24
is exposed.
Third, despite the provision of the 300 Å sacrificial oxide layer
22
beneath the polysilicon layer
24
, the underlying substrate
10
can nonetheless be easily damaged by the bombarding ions used in the ion-implantation process on the polysilicon layer
24
and by the plasma used in the selective etching process on the polysilicon layer
24
.
All the foregoing drawbacks cause undesired decreases in the charge breakdown (Q
BD
) and the breakdown voltage of gate oxide (BV
GOX
) of the subsequently formed gate oxide layer over the substrate. The resultant gate oxide layer is therefore degraded in electrical characteristics.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a resistor and a capacitor electrode in an integrated circuit which can help eliminate the above-mentioned drawbacks of the prior art so as to prevent the undesired decreases in the charge breakdown and the breakdown voltage of gate oxide of the subsequently formed gate oxide layer over the substrate.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabricating a resistor and a capacitor electrode in an integrated circuit is provided.
The method of the invention is proposed for use on an integrated circuit constructed on a semiconductor substrate that is already formed with a plurality of isolation structures defining a plurality of active regions with a silicon nitride layer formed over each of the active regions. The method of the invention comprises a first step of forming a polysilicon layer covering all the isolation structures and the active regions, the polysilicon layer being partitioned by definition into a resistor part and a capacitor electrode part. Then, optionally, a first oxide layer is formed over the polysilicon layer. Next, a first ion-implantation process is performed on the entire polysilicon layer to convert the entire polysilicon layer into a lightly-doped polysilicon layer with a first predefined impurity concentration. Then, a second ion-implantation process is performed solely on the predefined electrode part of the polysilicon layer so as to convert the electrode part of the polysilicon layer into a heavily-doped polysilicon layer with a second predefined impurity concentration higher than the first impurity concentration. Subsequently, a selective removal process is performed to remove selected parts of the lightly-do
Huang I-Ho
Huang Kuo-Liang
J.C. Patents
Kennedy Jennifer M.
United Microelectronics Corp.
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