Silicon chip built-in inductor structure

Details Silicon chip built-in inductor structure Silicon chip built-in inductor structure

2001-03-23

2002-04-16

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S379000, C257S509000, C257S516000, C257S528000, C257S544000, C257S647000, C257S648000

Reexamination Certificate

active

06373121

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a silicon chip built-in inductor structure. More particularly, the present invention relates to a type of field oxide inductor having an electrostatic shield underneath for stopping the circulation of eddy current inside a silicon substrate.
2. Description of Related Art
Due to cost considerations, most high frequency silicon chips have passive devices, such as inductors, formed therein. Because these inductors are formed close to the silicon substrate (often within 10 micrometers of the substrate), so a lot of energy is lost through the substrate during operation so that the quality factor (Q-factor) of the inductor may be reduced. Gallium-arsenic (GaAs) is a type of semiconductor material that has an insulating effect at high operating frequency. Therefore, expensive gallium-arsenic material instead of common silicon material is frequently used in the production of high frequency chips so that inductor performance is improved and energy is saved. However, the cost of gallium-arsenic is so overwhelming that the production cost of a complementary metal-oxide-silicon (CMOS) becomes relatively unimportant.
FIG. 1
is a schematic cross-sectional view of a conventional silicon chip with a built-in inductor thereon. As shown in
FIG. 1
, the structure includes a silicon substrate
100
divided into an active region
102
and an isolation region
104
. The active region
102
contains a plurality of active devices separated from each other by field oxide (FOX) layers within the isolation region
104
. A planarized dielectric layer
106
is formed over the active devices and the isolation region
104
. A built-in inductor
108
is formed over the dielectric layer
106
. The built-in inductor
108
includes multiple layers of induction coils
108
a
electrically isolated by dielectric layers
108
b
. In addition, various inductor coils
108
a
are electrically linked via plugs
108
c.
Since the inductor
108
is built on the isolation region
104
such as the field oxide (FOX) above the silicon chip
100
, electromagnetic induction during operation may produce an eddy current I inside the silicon substrate
100
. The eddy current I may flow along the axial direction of the inductor coil
108
a
. Consequently, the eddy current may lead to a drop in the Q-value of the inductor
108
. Ultimately, performance of the inductor
108
at high frequency is compromised.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a silicon chip built-in inductor structure. The built-in inductor is formed above a field device that comprises of an n-well, a field oxide (FOX) layer and a p-well underneath the field oxide layer. Because the deep p-n junction between the n-well and the p-well can provide an effective barrier for the flow of eddy current in the substrate, energy loss is greatly reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active device region and a region having grid-like field oxide devices. The grid-like field oxide region comprises of a plurality of field oxide layers, a plurality of first-type-ion-doped regions underneath the field oxide layers and a plurality of second-type-ion-doped regions in the substrate between various field oxide layers. A plurality of junction regions are formed between the first-type-ion-doped regions and the second-type-ion-doped regions. The junction regions impede the flow of an eddy current along a prescribed direction. In addition, a dielectric layer is formed over the substrate covering the active devices and the field oxide devices. The inductor device is formed on the dielectric layer above the field oxide devices. Since the first-type-ion-doped region and the second-type-ion-doped region are positioned alternately and in parallel to each other within the substrate, their junctions establish a grid-like structure capable of stopping inductor induced eddy current flow inside the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5416356 (1995-05-01), Staudinger et al.
patent: 5559349 (1996-09-01), Cricchi et al.
patent: 5930637 (1999-07-01), Chuang et al.
patent: 5994738 (1999-11-01), Wollesen
patent: 6002161 (1999-12-01), Yamazaki
patent: 6201289 (2001-03-01), Jou
patent: 6326673 (2001-12-01), Liou

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