Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-02-28
2002-04-16
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S374000, C326S062000, C326S068000, C326S080000
Reexamination Certificate
active
06373315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to signal potential conversion circuits. In particular, the invention relates to a signal potential conversion circuit converting a first signal having one level of a first potential and the other level of a reference potential into a second signal hating one level of a second potential different from the first potential and the other level of the reference potential.
2. Description of the Background Art
A semiconductor integrated circuit device has been provided with a signal potential conversion circuit for converting a signal potential into another signal potential. For example, a dynamic random access memory (hereinafter referred to as DRAM) has memory cells each including an N channel MOS transistor for access and a capacitor for information storage. Data of “H” (logical high) level (power supply potential VDD) or “L” (logical low) level (ground potential GND) is written into the capacitor. Data is written into/read from the capacitor via the N channel MOS transistor. In data writing/reading, for the purpose of preventing voltage drop in the N channel MOS transistor, a boosted potential (VPP) higher than the supply potential VDD is applied to the gate of the N channel MOS transistor. Peripheral control circuitry for writing/reading of data is driven by the supply voltage VDD. Therefore, in order to transmit a signal from the peripheral control circuitry to a memory cell, a signal potential conversion circuit is required to convert the supply potential VDD into the boosted potential VPP.
FIG. 10
is a circuit diagram showing a structure of such a signal potential conversion circuit. Referring to
FIG. 10
, the signal potential conversion circuit includes inverters
31
-
33
, P channel MOS transistors
34
and
35
, and N channel MOS transistors
36
and
37
.
P channel MOS transistors
34
and
35
are connected respectively between a line of the boosted potential VPP and nodes N
34
and N
35
, having respective gates connected to nodes N
35
and N
34
respectively. N channel MOS transistors
36
and
37
are connected respectively between nodes N
34
and N
35
and a line of the ground potential GND. An input signal VI is supplied to the gate of N channel MOS transistor
36
via inverter
31
and supplied to the gate of N channel MOS transistor
37
via inverters
31
and
32
. A signal appearing on node N
35
is inverted by inverter
33
and output as an output signal VO.
Inverters
31
and
32
each include a P channel MOS transistor and an N channel MOS transistor connected in series between a line of the supply potential VDD and the line of the ground potential GND, outputting a signal of L level in response to input of a signal of H level and outputting a signal of H level in response to input of a signal of L level.
Inverter
33
includes a P channel MOS transistor and an N channel MOS transistor connected in series between the line of the boosted potential VPP and the line of the ground potential GND, outputting a signal of L level in response to input of a signal of the boosted potential VPP and outputting a signal of the boosted potential VPP in response to input of a signal of L level.
FIG. 11
is a timing chart showing an operation of the signal potential conversion circuit shown in FIG.
10
. In the initial state, input signal VI, an output signal &phgr;
32
from inverter
32
, node N
34
and output signal VO are all at L level, an output signal &phgr;
31
from inverter
31
is at H level and node N
35
is at the boosted potential VPP. At this time, MOS transistors
35
and
36
are conductive while MOS transistors
34
and
37
are nonconductive.
When input signal VI rises from L level to H level at a certain time, signal &phgr;
31
falls to L level to turn off N channel MOS transistor
36
and signal &phgr;
32
rises to H level to turn on N channel MOS transistor
37
. Accordingly, the potential on node N
35
gradually decreases. When this potential becomes lower than VPP−|Vthp| (Vthp is the threshold voltage of the P channel MOS transistor), P channel MOS transistor
34
is turned on and node N
34
rises to the boosted potential VPP. When node N
34
reaches the boosted potential VPP, P channel MOS transistor
35
is turned off, node N
35
falls to L level, and output signal VO rises to the boosted potential VPP.
Following this, when input signal VI falls from H level to L level, signal &phgr;
31
rises to H level to turn on N channel MOS transistor
36
and signal &phgr;
32
falls to L level to turn off N channel MOS transistor
37
. Accordingly, the potential on node N
34
gradually decreases. When this potential becomes lower than VPP−|Vthp|, P channel MOS transistor
35
is turned on and node N
35
rises to the boosted potential VPP. When node N
35
reaches the boosted potential VPP, P channel MOS transistor
34
is turned off, node N
34
falls to L level, and output signal VO falls to L level.
In order to achieve reduced power consumption and enhanced speed of semiconductor integrated circuit devices, reduction of a power supply voltage thereof is now proceeding. Reduction of a power supply voltage of the DRAM is also in progress. However, reduction of the voltage for circuit components related to reading/writing of data from/into a memory cell cannot be promoted because of the necessity of maintaining a high-speed operation. Consequently, the difference between the voltage level of the peripheral control circuitry and the voltage level of the circuit components related to reading/writing of a memory cell is likely to become greater so that the difference between the input voltage VDD and the output voltage VPP of the signal potential conversion circuit tends to increase.
Regarding the conventional signal potential conversion circuit, node N
34
should be charged to VPP−|Vthp| or higher for turning off P channel MOS transistor
35
when input signal VI rises from L level to H level. If the potential difference between the boosted potential VPP and the supply potential VDD becomes greater, the off level VPP−|Vthp| of N channel MOS transistor N
35
becomes higher and accordingly charging of node N
34
to VPP−|Vthp| takes a longer time. In other words, a problem of the conventional signal potential conversion circuit is that the increased difference between the input voltage VDD and the output voltage VPP prolongs the time required to convert a signal potential.
Although node N
34
can be charged speedily by increasing the gate width of P channel MOS transistor
34
to enhance the current drive ability of P channel MOS transistor
34
, discharging of node N
34
to L level takes a longer time. Therefore, regarding the conventional signal potential conversion circuit, the time required for converting a signal potential cannot be shortened for both of the cases in which input signal VI rises from L level to H level and in which input signal VI falls from H level to L level.
SUMMARY OF THE INVENTION
One object of the present invention is accordingly to provide a signal potential conversion circuit capable of converting a signal potential speedily.
According to the present invention, a signal potential conversion circuit includes a discharge circuit discharging, in response to change of a first signal from a first potential to a reference potential, a first output node to the reference potential, the first output node provided for outputting a second signal, and discharging, in response to change of the first signal from the reference potential to the first potential, a second output node to the reference potential, the second output node provided for outputting a complementary signal of the second signal. The signal potential conversion circuit further includes a charge circuit including a first transistor and a second transistor having respective first electrodes both connected to a line of a second potential, respective second electrodes connected to the first and second output
Ooishi Tsukasa
Tomishima Shigeki
Tsuji Takaharu
Luu An T.
Mitsubishi Denki & Kabushiki Kaisha
Wells Kenneth B.
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