Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-05-07
2002-09-17
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S724000, C438S740000, C438S692000, C438S745000
Reexamination Certificate
active
06451704
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of performing p-type implantation in the Lightly Doped Diffusion (PLDD) area of a gate electrode, preventing diffusion of boron as the p-type impurity. This more specifically for gate electrodes with submicron channel length.
(2) Description of the Prior Art
Semiconductor technology has for many years made progress by a continued effort to decrease device dimensions in order to improve Integrated Circuit (IC) device performance. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices form an increasing percentage of the total number of devices that are used in Integrated Circuit (IC) applications. MOSFET devices are expected to continue to increase in importance, it is expected that by the year 2000 MOSFET devices will constitute roughly 90% of the overall market. Reduction in device dimensions results in a reduction in device power consumption. It is an accepted rule in semiconductor technology that device speed varies inversely with the length of device features, device power consumption increases approximately with the square of the device feature length. Current semiconductor technology approaches feature size in the micron and sub-micron or 0.5 &mgr;m range where a number of applications already use feature size of about 0.2 &mgr;m.
Field Effect Transistors (FET) are used extensively in Ultra Large Scale Integration (ULSI) applications. FET devices are formed using gate electrodes, usually made of polysilicon, and adjacent self-aligned source/drain regions to which source/drain contact surfaces are established. In its basic form, a Metal Oxide Semiconductor (MOS) transistor has a gate electrode to which a voltage is applied. The gate is created on the surface of a silicon substrate, the voltage that is applied to the gate creates an electric field that is perpendicular to the interface between the gate electrode and the substrate. The areas in the substrate immediately adjacent to the gate electrode are doped, thereby varying their electric conductivity. These areas become the source and drain regions. By varying the voltage that is applied to the gate electrode, the electric field in the interface between the gate and the substrate can be varied and, with that, the current that flows between the source and the drain regions. This electric field controls the flow of current through the device from which the name of Field Effect Transistor has been derived.
The type of device that is created and the type of areas that are created in conjunction with the device are to a large extent determined by the type of dopant that is used and the processing conditions under which the dopants are applied. The creation of semiconductor devices typically starts with a bare monocrystalline silicon substrate, which is any material that can retain dopant ions. Isolated active regions are created in the surface of the substrate. The silicon substrate further receives p-type or n-type ions (impurity implants) for the creation of various conductivity regions in or on the surface of the substrate. The device features that are created in or on the surface of the substrate dictate the type of doping and the doping conditions. For instance, boron or phosphorous can be used as respectively p-type and n-type dopants and can be doped into polysilicon layers or into polycide gate electrodes.
MOS devices are typically created on the surface of a substrate after either a p-type or a n-type impurity has been implanted in the surface of the substrate, creating wells in this surface of either p-type or n-type conductivity. NMOS devices (also referred to as n-channel devices) are, after that, created on the surface of a p-type well, PMOS devices (also referred to as p-channel devices) are created on the surface of an n-type well. The type of channel underlying a MOS gate electrode is determined by the type of conductivity of the channel that is developed under the transverse electric field of the gate electrode. Therefore, in an n-channel of NMOS devices, the conductivity of the channel underlying the transverse electrical field of the gate electrode is of the conductivity type that is associated with n-type impurities such as arsenic or phosphorous. For p-channel (PMOS) devices, these impurities comprise boron or indium. After the gate electrode has been created, Lightly Doped Diffusions (LDD) are typically implanted in the surface of the substrate, self aligned with the gate electrode, whereby n-type impurities are use for the LDD regions of NMOS devices and p-type impurities for the LDD regions of PMOS devices. After this, the gate electrode is isolated by the formation of gate spacers on the sidewalls of the gate electrode, this is followed by forming the source and drain regions of the gate electrodes. For the source/drain implants the same type impurities are used as have been used for the LDD implants, the difference between the LDD implants and the source/drain implants is that the source/drain implants are typically performed at higher implant energy and dosage that the LDD implants. In this manner the p-type implants (for PMOS devices) of the source/drain regions (PS/D) and the n-type implants (for NMOS devices) of the source/drain regions (NS/D) penetrate deeper into the surface of the substrate than the corresponding p-type (PLDD) and n-type (NLDD) implants for the LDD regions.
Dual gate transistor design is the design where both NMOS and PMOS devices are created on the same chip. Earlier designs of Metal Oxide Semiconductor (MOS) devices primarily used PMOS design because only with p-channel devices using n
+
-doped polysilicon gates and uniform lightly doped n-substrates could acceptable values for V
t
be attained. In its early history, the Complementary Metal Oxide Semiconductor (CMOS) transistor was considered to be only an extension of the design for MOS IC's. Later advancements in fabrication technology, mostly due to improvements in ion implant techniques, allowed for PMOS devices to be replaced with NMOS devices. The larger drive current of NMOS devices results in faster speed of these devices, which results in NMOS devices becoming the dominant type of device in the IC industry. NMOS devices however exhibited severe limitations in power density and power dissipation, causing CMOS devices to become the dominant technology for IC device manufacturing. With the arrival of CMOS devices, a renewed interest in PMOS devices developed. CMOS employs both NMOS and PMOS devices to form logic elements. The advantage of CMOS is that its logic devices draw significant current only during the transition from one logic state to the other while drawing very little current between this transition.
The scaling of the CMOS devices in the sub-micrometer device range presents a major challenge. For the fabrication of pchannel and n-channel devices, n doped polysilicon gates are used resulting in functional asymmetry. A number of techniques have been used to assure that the p-channel and n-channel devices are completely symmetrical in their performance characteristics such as threshold voltages, device dimensions and doping while the p-channel device is, for ease of manufacturing, a surface channel device. These devices are made using undoped polysilicon for the gate structures that are simultaneously doped at the time that the source/drain regions of each type of device are implanted. This leads to special manufacturing problems caused by, among others, diffusion of impurity implants through the gate oxide into the channel region thereby changing the threshold voltage of the device. Another concern in creating dual-gate CMOS devices is that various dopants may inter-diffuse between adjacent regions, an effect that can become critical at high anneal and other processing temperatures.
Increased CMOS device speed however requires short channel length, the design of p-channel devices with short channel length presents unique probl
Chivukula Subrahmanyam
Mukhopdhyay Madhudsudan
Pradeep Yelehanka Ramachandramurthy
Ye Jie
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Powell William A.
Saile George O.
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