Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1999-06-15
2002-06-11
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S010000, C712S014000, C712S016000, C345S215000
Reexamination Certificate
active
06405301
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a data-processing arrangement comprising a plurality of data processors for carrying out operations in parallel, an operation carried out by a processor being defined by an instruction word supplied to the data processor.
BACKGROUND ART
European patent application publication number 0,373,714 describes a data processor comprising a plurality of parallel-operating processor elements. The data processor further comprises a program memory for each processor element. The program memories contain micro-instructions. An activated micro-instruction controls the operation in the processor element. The program memories are connected to two lines. On these lines a reset signal can appear for the memory so that for example an address counter is set to an initial position. The starting of the various program is thus synchronized. On this connection there may also appear initialization information whereby a given memory can be addressed and subsequently filled with program information.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a data-processing arrangement which yields a better cost-efficiency.
The invention takes the following aspects into consideration. A data-processing arrangement usually carries out a certain data processing function in a series processing steps. In a processing step, each processor carries out a particular operation. Thus, in each processing step, there is an instruction word for each processor. A composition of instruction words applied in a processing step can be regarded as a very long instruction word (VLIW).
In the background art, there is a program memory for each processor element and each program memory contains an instruction word for each processing step. That is, the program memories taken as a whole comprise a VLIW for each processing step. Accordingly, the program memories will have a relatively large size and, therefore, they will be relatively costly. This particularly applies if the number of processing steps is relatively large or if the number of processors is relatively large and, even more, if both are large.
What is more, since the program memories in the background art have a relatively large size, it may not be possible to implement them together with the data-processing elements on a single integrated circuit. A bus system will be needed between the program memories and an integrated circuit which comprises the data-processing elements. The bus system will need to carry a VLIW with each processing step. Consequently, the bus system will need to carry a relatively large amount of data per unit of time. The bus system will therefore be relatively expensive.
According to the invention, the data-processing arrangement comprises a control processor for making compositions of instruction words on the basis of instruction-word composing software. A composition of instruction words defines operations which are carried out in parallel. That is, a composition of control words constitutes a VLIW.
Storage of instruction-word composing software will generally require less memory space than storage of VLIW-s as such. The cost-saving this provides will generally outweigh the additional costs associated to a control processor for making compositions of instruction words. Thus, the invention yields a better cost-efficiency.
The invention particularly yields a better cost-efficiency if the data-processing arrangement is in the form of an integrated circuit. This implies that the control processor forms part of the integrated circuit and, thus, that VLIW-s are generated within the integrated circuit. Consequently, any bus system between an external memory and the integrated circuit need not carry VLIW-s. This relaxes requirements on the bus system in terms of bandwidth which contributes to cost-efficiency.
An other advantage of the invention relates to the following aspects. A series of VLIW-s which are successively supplied to the data-processors determines the data processing function which the data-processing arrangement carries out. Let it be assumed that the data-processing arrangement has to carry out a different data processing function. In that case, a new series of VLIW-s has to be supplied to the data processors. If the VLIW-s as such are stored in a program memory, like in the background art, the series of VLIW-s in the program memory needs to be replaced by the new series of VLIW-s. This will generally be labor intensive and time consuming. In contrast, in the invention, only the instruction-word composing program needs to be replaced by a new instruction-word composing program. This will generally be less labor intensive and time consuming than replacing the series of VLIW-s as such. Thus, the invention allows a greater ease-of-use.
The invention and additional features, which may be optionally used to implement the invention to advantage, are apparent from and will be elucidated with reference to the drawings described hereinafter.
REFERENCES:
patent: 5649135 (1997-07-01), Pechanck et al.
patent: 5787302 (1998-08-01), Hampapuram et al.
patent: 6101592 (2000-08-01), Pechanck et al.
patent: 6173389 (2001-01-01), Pechanck et al.
patent: 0373714 (1990-06-01), None
Treat William M.
U.S. Philips Corporation
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