Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate
2000-11-10
2002-05-07
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
C375S362000, C375S377000
Reexamination Certificate
active
06385263
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of serial data transmission as it applies to computerized semiconductor devices and pertains more particularly to methods and apparatus for achieving high speed serial data transmission between semiconductor devices.
BACKGROUND OF THE INVENTION
The art of designing and implementing very large scale integration (VLSI) devices has become more complex and sophisticated in recent years. Sophisticated software design tools and automated techniques have replaced prior pencil and paper engineering practices once used to design semiconductor devices. As VSLI devices have become more complex in terms of circuitry and design with shrinking device geometry, requirements for data transmission between such devices have also become more complex and demanding to maintain in operation.
The preferred system used for data transmission between VLSI and other IC devices has long been the system of parallel data transfer. The current parallel method of passing data between such devices incorporates the use of a plurality of separate data-signal transmission paths in parallel. Data passed between two communicating devices travels across a circuit board on a plurality of parallel traces or lines. For a 16-bit system, for example, there will be in a parallel system a separate trace for each bit (16 traces) plus control lines.
Generally speaking, much operational and specification data regarding the manufacture and operation of VLSI type devices is known and available in the art. Manufacturers of such devices provide exhaustive documentation, and virtually all such documentation are available to the skilled artisan. Therefore detailed architectural and functional descriptions of known VLSI-type devices are not provided herein. It is enough to say that parallel data must be clocked, synchronized and latched in order to enable successful transmission of the data from a propagating device to a receiving device over a circuit board containing a substantially large number of traces.
Another system for transferring data in general, and also sometimes used for transferring data between IC devices the serial system. The current art serial method of transferring high bandwidth data between VLSI devices involves the use of encoding and decoding circuits on each device to manipulate parallel data so that it may be transmitted serially across a circuit board from one device to another. For example, a parallel to serial data converter in a sending device enables data to be prepared for transmission out in a serial manner using a single data line for one-way transmission. A decoder circuit in a receiving device decodes the serial data using a predetermined decoding scheme then processes the data. Because, given a single clock speed for both, serial data transfer is typically slower than parallel transfer, a high-speed clock is typically used with the serial system to speed up transmission of serial data between devices.
Another problem with serial data transfer between IC devices in current technology is that analog circuitry is typically required in the IC devices to effect the system. Analog circuitry is known to be notoriously more difficult to implement than digital circuitry, and makers of digital IC devices are not anxious to suffer the yield losses attendant on adding analog circuitry to their devices.
Still, even with the known and perceived disadvantages of serial data transmission, the high cost and complexity of parallel systems is an increasing problem. As computing systems have matured from 4 to 8 to 16 to 32 bit words, and as microprocessors and memories (for example) have become more functional and sophisticated, the number of traces and pins necessary to accomplish adequate transmission has increased dramatically. It is, for example, common now to have plural sets of parallel data transmission pathways serving a single IC device. The high number of traces necessary on a PC board (for example) makes such support systems enormously complex and expensive to design and manufacture. Moreover, every trace demands a separate pin on the IC device. Many devices have more than two hundred pins, and future devices may demand even more. The higher and higher pin count makes such devices more complex to build and increases losses (yield) in fabrication.
Another limitation relates to precious design space. For example, increasing the number of parallel devices complicates the physical connection scheme between a propagating device and a receiving device on a circuit board. Furthermore, the propagation delay of each data path from line to line must be kept common to ensure successful data reception. Adding to many traces may cause a significant variance in individual propagation delays leading to errors in data flow.
Other problems associated with adding additional data traces to facilitate parallel transmission of more data over a shorter period include increased electromagnetic emissions to adjacent circuitry and increased power requirements needed to support the hardware. Increased emissions may infect adjacent signal lines causing noise and increasing the possibility of data errors. Increasing power requirements reduces chip reliability and may require additional power-dissipation devices to be included in chip manufacture.
It is a goal in chip design to be able to transmit more data at higher rates. However, achieving this objective using parallel data transfer techniques creates complexity and added cost. It is well known that the current-art serial methods reduce the number of required data traces for data transmission. However, the complex analog circuitry required to achieve a comparable result with the parallel method at higher clock speeds presents technical obstacles related to the complex nature of the added circuitry, which ultimately lends leads to error prone data transmission.
Therefore, what is clearly needed is a method and apparatus that enables a high-speed serial intercommunication between VLSI and other semiconductor devices, fast enough to compete with at least present day parallel systems, and in a manner to overcome the complex issues in the art described above. Such a method and apparatus will provide a serial data transmission system that is competitive to the parallel system at high clock speeds, and will reduce the design complexity related to the physical connection scheme required between devices.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention a serial data communication system for communication between a first and a second IC device is provided, comprising a separate master chip connected to both the first and to the second IC devices, the master chip comprising a clock generator and circuitry for affecting serial data transmission and control between the master chip and the first and second IC devices; and a slave component on each IC device for transforming data between parallel and serial data formats and for sending and receiving a serial data stream. The master chip provides a clock signal to both slave components for gating serial data communication, and manages all communication between the two slave components. Preferably all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip.
In one embodiment of the invention each slave component sends a serial data stream to the master chip for transfer to the opposite slave component, receives serial data stream from the master chip provided by the opposite slave component, and compares phase between the serial data stream received and the clock signal. Upon detecting a phase difference between the clock signal and the serial data stream received, each slave component sends a correction code in the serial data stream sent to the master chip, the correction code indicating a correction in phase to be made between the clock signal and the serial data stream received by the slave component. Upon receiving the correction code the master chip causes a correction to be made in the phase bet
Bowers Richard
Evans Kelvyn
Measor Grahame
Boys Donald R.
Central Coast Patent Agency Inc.
Hiband Semiconductor, Inc.
Tse Young T.
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