Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-06-26
2002-07-30
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000, C341S155000, C341S172000, C341S118000, C341S120000
Reexamination Certificate
active
06426714
ABSTRACT:
TECHNICAL FIELD
These teachings relate generally to analog-to-digital converter (ADC) circuitry and, more specifically, to sigma-delta (SD) modulators (SDMs), in particular multibit SDMs.
BACKGROUND
SD modulators used in ADCs and other applications are well known in the art. Reference may be had, by example, to S. R. Norsworthy et al., “Delta-Sigma Data Converters”, IEEE Press, NY, 1997, and to J. G. Proakis et al., “Digital Signal Processing” Third Edition, Prentice-Hall, 1996. A typical embodiment of a SD modulator includes a loop filter followed by quantizer, and a digital-to-analog converter (DAC) in the feedback path.
Single-bit SD modulators are widely used in analog-to-digital converters (ADC) because they do not require accurate components, and can thus be readily implemented using modern CMOS processes. The single-bit DAC in the feedback loop is particularly easy to implement, as it is inherently linear. However, to achieve a high dynamic range the single-bit modulator requires a high oversampling ratio (OSR) or modulator order, which may result in a prohibitively large integrated circuit area and/or current consumption. The OSR and/or modulator order can be reduced by increasing the number of quantization levels, i.e. by using a multi-bit (MB) modulator, However, this approach requires a multibit DAC in the feedback loop and, since multibit DACs are not inherently linear, to achieve high accuracy (e.g., greater than 10 or 11 bits) either calibration or dynamic element matching (DEM) is often required.
Generally, multibit DACs are linearized with calibration techniques, or the effects caused by the nonlinearity of the multibit DAC are reduced with DEM circuitry implemented with conventional digital logic.
In the modern and emerging mobile communications protocols and systems, such as GSM/EDGE and WCDMA, stringent requirements (dynamic range and/or sampling frequency) are placed on the analog-to-digital conversion. In addition, multimode operation is often required, and the use of common hardware in the various modes is highly desirable, especially from the standpoint of making efficient use of integrated circuit area.
One of the strengths of the sigma-delta modulator technique is that there are several ways in which to configure the sigma-delta modulator to meet the required specifications. For example, the OSR, the modulator order and the number of quantization levels may all be varied depending on the application or mode of operation.
Furthermore, in order to fully exploit the benefits of modern digital signal processing during multimode operation, it is often desirable to use common radio frequency (RF) and analog baseband circuitry in all of the operational modes, and to then perform all protocol and system-specific functions in the digital domain. This places even higher requirements on the dynamic range and sampling frequency of the analog-to-digital converter. In addition, if the dynamic range and bandwidth of the analog-to-digital conversion can be made sufficiently large, it may be possible to eliminate some of the RF and analog baseband blocks, such as filters and variable gain amplifiers, thereby realizing further savings in cost, circuit area and power consumption.
As was noted above, to achieve a wide dynamic range single-bit modulators require a high OSR and/or modulator order, which may lead to a prohibitively large circuit area and/or current consumption. The OSR and the modulator order can be reduced by increasing the number of quantization levels, i.e. by using the multibit SD modulator. However, the use of multibit SD modulator introduces other problems, such as the nonlinearity of the feedback path SD modulator DAC caused by component mismatches.
SUMMARY
The foregoing and other problems are overcome by methods and apparatus in accordance with embodiments of these teachings.
A multilevel quantizer is provided in combination with dynamic element matching (DEM) circuitry in a multibit sigma-delta modulator. The DEM circuitry is implemented in an integrated circuit area and power efficient manner, and is also implemented so as to relax the strict timing constraints imposed on the operation of the DEM circuitry. The timing constraints arise from the fact that the sigma-delta modulator is a feedback system, and the DEM circuitry is a component part of the feedback loop.
In accordance with these teachings the DEM circuitry is divided into two major component parts: at least one DEM switch matrix (SM), preferably a current mode DEM switching matrix, and an associated DEM decision logic block that implements the DEM control algorithm and that controls the DEM SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. In this manner the DEM decision logic block has more time to implement the DEM algorithm, which in turn gives more freedom and flexibility in the design of the DEM algorithm. One beneficial result is that, for example, a more complex DEM algorithm may be employed than would otherwise be possible.
Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N−1 digital output bits of the N-level quantizer.
The undesirable effect caused by the nonlinearity of the multibit DAC, i.e., the generation of spurious and harmonic tones, is reduced by using the DEM SM to rearrange the bits according to a suitable algorithm so that the tones are converted to frequency-shaped noise.
The timing constraints limiting the choice of the DEM algorithm are overcome by placing the DEM decision logic block, which implements the DEM algorithm, outside of the delay-sensitive SDM feedback loop. In this manner the throughput may still be one control word per clock phase, but more freedom is provided in the selection of the DEM algorithm, i.e. one may select a relatively simple DEM algorithm (e.g., random, cyclic, data weighted averaging (DWA), etc.) or a more complicated DEM algorithm (e.g., one based on sorting). The DEM algorithm may be programmably changed during operation to match the operating and signal conditions, as well as the mode of operation in a multimode communication device.
The required circuit area, power consumption and speed of the DEM SM are improved as well, as a compound quantizer/SM structure is simple and convenient to implement, and has the potential to reduce the area, power consumption and delay in the feedback loop, as compared to using a separate quantizer and SM. The preferred current steering logic used in the DEM SM is dense, compact and fast, and if implemented with minimum size transistors, the additional capacitive load, and therefore also the increase in the current consumption, is insignificant.
A method is also disclosed for operating a quantizer of a sigma-delta modulator. The method includes sampling and converting a quantizer input signal to a sampled current signal; adding a dither current signal to the sampled current signal to generate a dithered sampled current signal; coupling the dithered sampled current signal to an input terminal of individual ones of N−1 comparator stages; dividing the dithered sampled current signal equally amongst the N−1 comparator stages; operating individual ones of the N−1 comparator stages to compare a divided portion of the dithered sampled current signal to an associated one of N−1 reference current signals; and latching an output of each of the N−1 comparator stages with one of N−1 latches. The method further operates at least one dynamic element matching (DEM) switching matrix to reorder a multibit digital signal appearing at N−1 digital output terminals of a quantizer circuit under control of a DEM algorithm logic block.
In one embodiment the step of operating at least one DEM switching matrix includes reordering the N−1 reference current signals at inputs to the N−1
Ruha Antti
Ruotsalainen Tarmo
Tervaluoto Jussi-Pekka Tervaluoto
Harrington & Smith ,LLP
Mai Lam T.
Nokia Corporation
Wamsley Patrick
LandOfFree
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