Multi-layer wiring structure having continuous grain boundaries

Details Multi-layer wiring structure having continuous grain boundaries Multi-layer wiring structure having continuous grain boundaries

1994-04-14

1995-06-27

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257767, H01L 23532, H01L 29417

Patent

active

054282519

ABSTRACT:
In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface. This control may be done by suitably controlling the condition of sputter-etching the surface of the first wiring layer through the connection hole and the condition of sputtering the Al or Al alloy of tile second wiring layer.

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