Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-26
2002-07-23
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S226000
Reexamination Certificate
active
06424570
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to memory systems and in particular, to flash memory array systems and methods for producing a charge pump circuit, wherein a voltage detection circuit (e.g., analog to digital converter, digital thermometer), may be used to measure the V
CC
applied to the charge pump circuit, along with variable pumping capacitance network compensation circuitry to conserve power, and to reduce the ripple and noise in the output voltage. The modulated charge pump voltage may be applied to a wordline or bitline, for example, for program or erase mode operations of memory cells.
BACKGROUND OF THE INVENTION
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read or program operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
For a read operation, a certain voltage bias is applied across the drain and source of the cell transistor. The drain of the cell is coupled to the bitline, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between about 0.5 and 1.0 volts in a read operation. A voltage is then applied to the gate (e.g., via the respective wordline) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed cell threshold voltage (V
T
) and an unprogrammed cell threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
More recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The bitline (drain), and wordline (gate) voltages required for dual bit memory cells is typically higher than that of single bit, stacked gate architecture memory cells, due to the physical construction of the dual bit cell.
In these semiconductor applications, a charge pump sometimes is used to increase a small input, or supply voltage (for example, V
CC
) to a larger voltage that is passed to the word lines or bit lines of the semiconductor memory devices. For example, some dual bit memory cell architectures require about 9.5 volts to properly bias the word lines, about 6 volts for the bitline or drain of such cells, and between −6 to −8 volts for negative erase voltages, for the various memory operations discussed. These voltages which are all higher than the applied supply voltage, are all created and fed by charge pumps to increase the supply voltage to the output voltage desired. These voltages affect the reading and writing of data from/to the memory device. The voltage is increased by channeling the relatively small input voltage through a series of stages. The more stages a charge pump has, the greater the resulting output voltage.
Because these charge pump voltages applied to the memory cell are derived from the memory device supply voltage (V
CC
), the ability to provide the higher voltage required for the newer dual bit memory cells may be impaired when the supply voltage is at or near lower rated levels. In addition, low power applications for memory devices, such as cellular telephones, laptop computers, and the like, may further reduce the supply voltage available.
Currently, conventional charge pumps are constructed using several bootstrap capacitors having the same capacitance C at each respective node of the charge pump. A bootstrap capacitor is defined as the capacitor connected to each respective node of a charge pump. As the required voltages for applications increases, the number of stages necessary to generate the higher output voltages also increases. However, as the number of stages is increased, the efficiency of the charge pump has been found to decrease.
FIG. 1
provides an illustration of a conventional charge pump. As shown, the conventional charge pump
100
has a number of stages (stage
1
thru stage n). The charge pump
100
has at its input, a voltage, V
CC
which is transmitted through a diode
115
to a first node (node
1
) including a first bootstrap capacitor
120
having a capacitance C. A second node (node
2
) is connected to the first node (node
1
) via a diode
125
and also has a second bootstrap capacitor
130
having a capacitance C. The output of node
2
is then passed through a number of subsequent nodes, identical to previously described nodes
1
and
2
, that also include a bootstrap capacitor having a capacitance value C that is substantially identical to the capacitance value C present at nodes
1
and
2
. Finally, the conventional charge pump has an output terminal, V
OUT
, also having a capacitor
160
having a total capacitance C
L+P
which is defined as being the load capacitance C
L
of the load connected to the output of the pump and a parasitic capacitance C
P
inherent in the transmitting means of the conventional pump. As stated above, the bootstrap capacitance of the various nodes of circuit
100
in prior art
FIG. 1
all have value C.
In the prior art example of
FIG. 2
, a conventional two stage charge pump
200
is illustrated with large capacitor values to accommodate the lowest power supply level, and the addition of a shunt regulator
270
attached at the conventional point of the charge pump output
280
, to reduce the output when the supply or the output voltage is higher than a target value. As in
FIG. 1
, the charge pump
200
of
FIG. 2
includes an input
210
coupled to an input voltage such as the supply voltage V
CC
. The input
210
is coupled to a first stage, via a diode
215
, which is also coupled to a first stage node (node
1
) including a capacitor
220
having a capacitance C
1
.
The first stage is further connected to a second stage,
Chen Pau-Ling
Le Binh Q.
Eschweiler & Associates LLC
Zarabian A.
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