Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device
Reexamination Certificate
1999-08-02
2002-07-23
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
C257S173000
Reexamination Certificate
active
06423985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit techniques. More particularly, the present invention relates to a compact structure of semiconductor controlled rectifiers.
2. Description of the Related Art
Sub-micron CMOS ICs have become increasingly vulnerable to ESD damage due to advanced processes such as the use of lightly-doped drain structures and clad silicide diffusions. As a solution, lateral semiconductor-controlled rectifiers (LSCRs), disclosed in U.S. Pat. No. 5,012,317, have been employed as ESD protection circuits for shunting ESD stress. The top and cross-sectional views of the conventional LSCR are illustrated in
FIGS. 1 and 2
, respectively.
Referring to
FIGS. 1 and 2
, the LSCR is fabricated onto a P-type semiconductor substrate
10
, for example a silicon substrate, in a predetermined portion of which an N-well region
11
is formed. In addition, a P-type doped region
12
is formed within the extent of the N-well region
11
, and an N-type doped region
13
is formed within the extent of the P-type substrate
10
. Therefore, the LSCR is constituted by the P-type doped region
12
as an anode, the N-well region
11
as an anode gate, the P-type substrate
10
as a cathode gate, and the N-type doped region
13
as a cathode.
Moreover, an N-type contact region
14
and a P-type contact region
15
are formed within the N-well region
11
and the P-type substrate
10
as the ohmic contacts, respectively. Usually, the anode
12
and the contact region
14
are tied together to an integrated circuit pad (not shown in the drawing), while the cathode
13
and the contact region
15
are tied together to the V
SS
power node. The triggering of the conventional LSCR to activate and thus bypass the ESD stress relies heavily on whether the P/N junction between the P-type substrate
10
and the N-well region
11
enters avalanche breakdown.
U.S. Pat. No. 5,465,189 discloses a low voltage triggering SCR (LVTSCR) with a MOS-like device to reduce the trigger voltage within the range of about 10~15V. The top view and cross-sectional view of the conventional LVTSCR are illustrated in
FIGS. 3 and 4
, respectively.
As shown in
FIGS. 3 and 4
, the LVTSCR is fabricated onto a P-type semiconductor substrate
30
in which an N-well
31
is provided. In addition, a P-type doped region
32
is formed within the extent of the N-well region
31
, and an N-type doped region
33
is formed within the extent of the P-type substrate
30
. Therefore, an SCR is constituted by the P-type doped region
32
as an anode, the N-well region
31
as an anode gate, the P-type substrate
30
as a cathode gate, and the N-type doped region
33
as a cathode. Moreover, an N-type doped region
34
is provided with one portion formed in the N-well region
31
and other portion formed in the P-type substrate
30
so as to sit over the P/N junction therebetween. A gate structure
35
is provided to overlie a portion of P-type semiconductor substrate
30
between the N-type doped regions
33
and
34
.
Furthermore, an N-type contact region
36
and a P-type contact region
37
are formed within the N-well region
31
and the P-type substrate
30
as the ohmic contacts, respectively. Usually, the anode
32
and the contact region
36
are tied together to an integrated circuit pad (not shown in the drawing), while the cathode
33
and the contact region
37
are tied together to the V
SS
power node. However, the triggering of the conventional LVTSCR is determined by the P/N junction breakdown between the P-type substrate
30
and the N-type doped region
34
so that the trigger voltage can be reduced within the range of about 10~15V.
As mentioned above, the triggering of the SCR is primarily determined by avalanche breakdown occurring at the junction between the P-type substrate
10
and the N-well region
11
as shown in
FIG. 1
, or at the junction between the P-type substrate
30
and the N-type doped region
34
as shown in FIG.
3
. Therefore, the dimensions for the anode, cathode, and contact region of the SCR are not dominant factors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a compact structure of a semiconductor controlled rectifier to reduce the required layout area.
To achieve the above-identified object, the present invention provides an SCR structure having an N-type semiconductor layer, a P-type semiconductor layer in contact with the N-type semiconductor layer, an anode doped region, a cathode doped region, a first contact region and a second contact region. The anode doped region is formed in the N-type semiconductor layer, while the cathode doped region is formed in the P-type semiconductor layer. The first and second contact regions are formed in the N-type semiconductor layer and the P-type semiconductor layer, respectively. According to the present invention, at least one of the anode doped region and the cathode doped region is combined with one of the corresponding first and second contact regions.
Accordingly, because the triggering of the SCR to turn on and thus bypass ESD stress is principally determined by the junction width, the SCR structure of the present invention combines at least one of the anode doped region and the cathode doped region with the corresponding contact region into a common region so as to decrease the required layout area.
Moreover, the present invention provides an SCR structure, which comprises a floating N-type semiconductor layer, a P-type semiconductor layer in contact with the N-type semiconductor layer, an anode doped region, a cathode doped region, and a contact region. The anode doped region is formed in the N-type semiconductor layer, while the cathode doped region and the contact region are formed in the P-type semiconductor layer. According to the present invention, the cathode doped region is combined with the contact region to form a common region.
Accordingly, because the triggering of the SCR to turn on and thus bypass ESD stress is principally determined by the junction width, the SCR structure of the present invention combines the cathode doped region with the contact region into the common region so as to decrease the required layout area.
Furthermore, the present invention provide an SCR structure, which comprises a N-type semiconductor layer, a floating P-type semiconductor layer in contact with the N-type semiconductor layer, an anode doped region, a cathode doped region, and a contact region. The anode doped region and the contact region are formed in the N-type semiconductor layer, while the cathode doped region is formed in the P-type semiconductor layer. According to the present invention, the anode doped region is combined with the contact region to form a common region.
Accordingly, because the triggering of the SCR to turn on and thus bypass ESD stress is principally determined by the junction width, the SCR structure of the present invention combines the anode doped region with the contact region into the common region so as to decrease the required layout area.
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patent: 5012317 (1991-04-01), Rountre
patent: 5182220 (1993-01-01), Ker et al.
patent: 5452171 (1995-09-01), Metz et al.
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5721445 (1998-02-01), Singh et al.
patent: 5744840 (1998-04-01), Ng
patent: 5969400 (1999-10-01), Shinohe et al.
patent: 6061218 (2000-05-01), Ida et al.
patent: 10050936 (1998-02-01), None
Beyer Weaver & Thomas LLP
Flynn Nathan
Quinto Kevin
Winbond Electronics Corp.
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