Process of eliminating a shallow trench isolation divot

Details Process of eliminating a shallow trench isolation divot Process of eliminating a shallow trench isolation divot

2000-07-19

2002-05-21

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S296000, C438S426000, C438S431000, C257S506000, C257S510000

Reexamination Certificate

active

06391739

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a process of forming an isolation region in a semiconductor device, and more specifically to a process of fabricating a shallow trench isolation (STI) structure in a semiconductor device.
2. Description of the Prior Art
As semiconductor device dimensions decrease, and device density increases, it becomes more difficult to efficiently and reliably fabricate isolation structures for separating active areas of the device. One common method of forming isolation structures for semiconductor devices is referred to as localized oxidation of silicon (LOCOS). However, the limits of the standard LOCOS process have motivated the development of new isolation processes. A trench isolation process is now widely used as it uses a fully recessed oxide, has no bird's beaks, is fully planar, and does not suffer from field oxide thinning effects. However, trench isolation structures formed in accordance with conventional trench isolation processes still suffer from problems such as the well known “corners” effect problem which arises due to a divot being formed proximate the edge of the trench. This divot can increase device leakage current, especially when the trench is recessed, thereby causing the life of the semiconductor device to be shortened.
FIG. 1
shows a cross-sectional view of a typical prior art shallow trench isolation (STI) structure at
10
. The STI structure
10
is formed within and over a substrate
12
. In accordance with conventional processes of manufacturing an STI structure, a trench
14
is formed within the substrate
12
, and isolation material
16
commonly referred to as trench oxide material is deposited within the trench
14
. As mentioned above, a problem that arises in conventional shallow trench isolation processes is that a recess, or divot
18
is formed proximate the edge of the trench
14
. When the isolation material
16
is etched, the divot
18
results wherein little or no isolating material
16
remains at the “corners” of the trench
14
. The exposed “corners” are potential points of current leakage between active areas of the semiconductor device. In accordance with one conventional STI process, silicon oxide material
20
is formed within the divot
18
proximate the edge of the trench
14
. A layer (not shown) of silicon oxide is formed over the isolation material and over an exposed portion of the substrate, and the layer of silicon oxide is subsequently etched to leaving the silicon oxide material
20
within the divot
18
. However, a problem arises in that damage is caused to the substrate
12
during this step of etching to remove the silicon oxide layer (not shown) because no etch stop layer is used in this process.
FIG. 2
shows a cross-sectional view of a second prior art STI structure at
30
wherein the trench
18
is filled with silicon nitride material
32
. In accordance with a conventional process for forming the STI structure
30
, a pad oxide (not shown) is used as an etch stop layer. A subsequent process must be performed in order to remove the pad oxide resulting in a portion
34
of the trench oxide
16
being removed. Therefore, the top surface of the STI structure
10
is not planar because a silicon nitride bump is created. This increases leakage current between active areas of the device leading to device degradation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a process of fabricating a shallow trench isolation (STI) structure that provides for improved isolation between active areas of a semiconductor device, and which does not result in the substrate of the device being damaged.
Briefly, a presently preferred embodiment of the present invention includes a process of fabricating a shallow trench isolation structure including the steps of: providing a substrate; forming a first insulating layer over the substrate; forming a nitride masking layer over the first insulating layer; patterning and etching the nitride masking layer, the first insulating layer and the substrate to remove portions of the nitride masking layer, the first insulating layer and the substrate thereby forming an exposed trench in the substrate, the trench substantially defining boundaries of the isolation structure; depositing a second insulating layer into the trench and over the nitride masking layer; planarizing the second insulating layer to expose the nitride masking layer; removing the nitride masking layer to expose the first insulating layer, and forming a divot proximate an edge of the trench; depositing a silicon layer into the divot, and over the first insulating later and the second insulating layer; etching the silicon layer to expose the first insulating layer, a central portion of the second insulating layer, and leaving a remaining portion of the silicon layer filling the divot; and oxidizing the remaining portion of the silicon layer.
An important advantage of the process of fabricating an STI structure in accordance with the present invention is that it provides for improved isolation between active areas of a semiconductor device by eliminating the divot.
Another important advantage of the process of the present invention is that the substrate is protected by the first insulating layer which provides an etch stop layer during the step of etching the silicon layer. Therefore, the substrate is not damaged as a result of forming the STI structure.


REFERENCES:
patent: 5393694 (1995-02-01), Mathews
patent: 6130467 (2000-10-01), Bandyopadhyay

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