Prevention of die loss to chemical mechanical polishing

Details Prevention of die loss to chemical mechanical polishing Prevention of die loss to chemical mechanical polishing

1999-08-19

2002-09-03

Rosasco, S. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Radiation modifying product or process of making

Radiation mask

C430S022000, C438S942000

Reexamination Certificate

active

06444371

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Technical Field
This invention relates generally to an apparatus and method for making integrated circuits and more particularly, the invention relates to methods that prevent die loss resulting from planarization using chemical mechanical polishing.
(2) Description of the Prior Art
The following four documents relate to methods dealing with chemical mechanical polishing of integrated circuits formed on semiconductor wafers.
U.S. Pat. No. 5,271,798 issued Dec. 21, 1993 to G.Sandhu et al., remedies the problems associated with selective etching of material, in particular tungsten, by locally removing the material, e.g. tungsten, from the alignment marks through wet etching without the need for any photo steps. Either before or after chemical mechanical polishing, the wafers are flatly aligned and a tungsten etching agent is introduced through an etching dispensing apparatus onto the alignment marks. U.S. Pat. No. 5,362,669 issued Nov. 8, 1994 to J.Boyd et al., discloses a method of chemical mechanical polishing using polish stops in wide trenches.
U.S. Pat. No. 5,401,691 issued Mar. 28, 1995 to Caldwell, shows a method of forming an alignment mark using an inverse open frame.
U.S. Pat. No. 5,627,110 issued to Lee et al. shows a method for eliminating a window mask process in the fabrication of a semiconductor wafer when chemical mechanical polish planarization is used.
The fabrication of integrated circuits on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic photomasks onto the wafer. The photomasking processing steps open selected areas to be exposed on the wafer for subsequent processes such as inclusion of impurities, oxidation, or etching.
During the forming of integrated circuit structures, it has become increasingly important to provide structures having multiple metallization layers due to the continuing miniaturization of the circuit elements in the structure. Each of the metal layers is typically separated from another metal layer by an insulation layer, such as an oxide layer. To enhance the quality of an overlying metallization layer, one without discontinuities of other blemishes, it is imperative to provide an underlying surface for the metallization layer that is ideally planar. The process of planarizing is now a standard process application of integrated circuit manufacturers.
Plasma, or reactive ion etching of the oxide layers having a resist planarizing medium, are conventional planarization techniques that are used to provide a smooth surface and a local planarization with a range of 1 &mgr;m.
To meet the demand for larger scale integration, and more metal and oxide layers in devices and the exacting depth of focus needed for submicron lithography, a new planarization method, known as chemical mechanical polishing (CMP), was developed and is presently used by most major semiconductor manufacturers. CMP planarization of a wafer involves supporting and holding the wafer against a rotating polishing pad wet with a polishing slurry and at the same time applying pressure. Unlike the conventional planarization techniques, CMP provides a substantially improved overall planarization, that is, an improvement of 2 to 3 orders of magnitude over conventional methods. Although CMP planarization is effective, die loss still occurs. Referring now to
FIGS. 1
a
and
1
b
, the problem associated with present CMP planarization is a “high plateau” effect, surrounding alignment targets
11
,
12
and the outside periphery
21
of the die array
20
which can cause a non-uniform polishing of the substrate surface. Stepping fields
15
,
16
and
21
are skipped during alignment and exposure of substrate
10
, the photoresist layers over blank stepping fields
15
,
16
and
21
are never exposed during the process. Thus, all layers deposited on substrate
10
are always deposited over blank stepping fields
15
,
16
and
21
but are never removed or etched away. The blank stepping fields
15
,
16
and
21
, therefore, consists of the worse case (highest) elevation structure on the wafer.
As noted, the build up of the deposited materials on the blank stepping fields
15
,
16
and
21
appears to the polisher as a high plateau area. Since the area is large and flat, the polish rate of blank stepping fields
15
,
16
and
21
is slow, like that of a blank wafer. The high plateau of the blank stepping fields lowers the polish rate of the edges of the IC die
20
which immediately surround blank stepping field
15
,
16
and the wafers edge
21
. The high plateau effect, therefore, can cause an unacceptable yield falloff on die which border blank stepping fields.
As a result, the prior art technique has difficulty in providing trouble free device patterns causing open contact or via and thus, causes a problem that the process margin in fabricating semiconductor devices is reduced, so as to lower production yield.
SUMMARY OF THE INVENTION
The present invention seeks to provide a method of forming integrated circuits using planarization by chemical mechanical polishing, which avoids the above-mentioned problem.
According to one aspect of the present invention, there is provided a novel process for preventing die losses that are contiguous to the die containing the alignment targets when a CMP planarization process is used. It is an object of the present invention to show how to use the immediate area surrounding the alignment targets for forming die topology to reduce the deleterious effects of open area polishing to the alignment target's neighboring devices during CMP planarization.
It is another object of the present invention to provide the method for making use of the immediate area surrounding the die array for forming die topology to reduce the deleterious effects of open area polishing to neighboring devices during CMP planarization.
It is still another object of the present invention to provide the method capable of high yield in fabricating a semiconductor device.
It is an additional object of the present invention to provide the method, useful in a semiconductor device having large scale integration.
Based on the intensive and thorough research and study by the present inventors, the above objects can be accomplished. In accordance with these aims and aspects, the present invention is concerned with providing a method for processing and forming integrated circuits on a wafer which is to have an array of integrated circuit dice and at least two of the dice reserved for alignment targets formed therein. The method of the invention includes the forming of topologic features adjacent the alignment targets and within its reserved die area, also, adjacent and surrounding the outer most dice of the integrated circuit dice array The topologic features will be included in the set of photomasks during the photolithographic process which opens selected areas for exposure for subsequent layering such as etching, oxidation, and metallization. The topologic features are also planarized during the CMP process. This novel approach “breaks-up” the otherwise open/unused areas adjacent IC dice thus preventing yield losses caused by CMP planarization. The topologic features are disposed between the alignment targets and IC die as illustrated in
FIGS. 2
a
and
2
b
. The features comprise strips
25
,
26
in the Y—Y direction and a plurality of clear-out windows in the X—X direction.
DESCRIPTION OF THE DRAWINGS
FIG. 1
a
is an illustration of an overhead view of a semiconductor wafer of the prior art.
FIG. 1
b
is an exploded view of a void stepping field of the prior art.
FIG. 2
a
; is an illustration of an overhead view of a semiconductor wafer of the invention.
FIG. 2
b
is an exploded view of a void stepping field of the invention.
FIG. 2
c
is a partial and exploded view of a semiconductor wafer of the invention.
FIG. 3
illustrates a photomask reticle having the topological features of the invention.
FIG. 4
a
illustrates a top view of a test sample having a left and a right alignment target d

Affiliated with

Also associated with

Rating

Prevention of die loss to chemical mechanical polishing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Prevention of die loss to chemical mechanical polishing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Prevention of die loss to chemical mechanical polishing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2888319