Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-19
2002-05-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290
Reexamination Certificate
active
06385090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor nonvolatile memory, which utilizes floating gates, and more particularly to semiconductor nonvolatile memory, which eliminates delay in erase operation and reduces stress on a tunnel dielectric layer.
2. Description of the Related Art
A semiconductor nonvolatile memory, which makes use of floating gates, is electrically rewritable, can retain data even in the power OFF state, and is widely used as flash memory.
FIG. 1
is a diagram showing the cell structure of a conventional semiconductor nonvolatile memory.
FIG. 1A
is an erase state, in which data “0” is stored.
FIG. 1B
is a programmed state (written state), in which data “1” is stored. As for the cell structure, an n-type source region
11
and drain region
12
are formed at the surface of a p-type semiconductor substrate
10
, a floating gate FG is formed via a tunnel dielectric layer (normally an oxide layer) above the channel region therebetween, and, in addition, a control gate CG is formed via a dielectric layer thereabove.
When a charge, such as electrons, is not stored in a floating gate FG, it is an erased state, in which the threshold voltage of a cell transistor is low, and data “0” is stored. In this state, when a prescribed read-out voltage is applied to the control gate CG, the cell transistor conducts. Conversely, when a charge, such as electrons, is stored in the floating gate FG, it is a programmed state, in which the threshold voltage of a cell transistor is high, and data “1” is stored. In this state, even if a read-out voltage is applied to the control gate CG, the cell transistor does not conduct. Data determination is performed in accordance with a cell current, which is generated by the conduction and non-conduction of the cell transistor. Furthermore, for the sake of brevity, examples will be explained hereinbelow using electrons as the charge stored on a floating gate.
The writing (programming) and erasing of data are performed by injecting and extracting electrons into and from a floating gate FG via a tunnel dielectric layer
13
. In a write operation (programming operation), for a cell in an erased state, hot electrons are generated in the channel region by applying 10 V, for example, to the control gate CG, 5 V, for example, to the drain
12
, and 0 V, for example, to the source
11
, and the hot electrons thereof are injected into the floating gate FG by an electric field resulting from the positive voltage applied to the control gate CG. Determining whether or not write is complete is performed by applying a prescribed program verify voltage to the control gate, and checking cell current in accordance with the conduction, non-conduction of the cell transistor.
In an erase operation, for a cell in a programmed state, −10 V, for example, is applied to the control gate CG, the drain
12
is set to the floating state, and 5 V, for example, is applied to the source
11
as well. In accordance therewith, a high electric field is generated in the tunnel dielectric layer
13
, and electrons in the floating gate FG tunnel through the tunnel dielectric layer
13
by the FN (Fowler-Nordheim) tunneling effect, and are extracted to the source
11
. Determining whether or not erase is complete is-performed by applying a prescribed erase verify voltage to the control gate, and checking cell current in accordance with the conduction, non-conduction of the cell transistor.
An erase operation is generally not performed in memory cell units, but rather, is performed collectively in either block units or chip units comprising a plurality of memory cells. Thus, in an erase operation, all cells are initially set to the written state (programmed state). Thereafter, the above-mentioned erase operation is performed for all memory cells. Further, an erase operation is performed while carrying out erase verify each time an erase pulse is applied.
A read-out operation is performed by applying 5 V, for example, to the control gate of a selected memory cell, 1 V, for example, to the drain, and 0 V, for example, to the source, and checking the conduction
on-conduction of the cell transistor. As for the voltage applied to the control gate, an intermediate value of the threshold voltages of the erased state and programmed state (written state) is selected.
In the above-mentioned erase operation, a large number of electrons remain on a floating gate at the start of erase operation. Therefore, when −10 V is applied to the control gate, the potential resulting from the electrons on the floating gate is increased, and an excessive electric field is applied to the tunnel dielectric layer
13
. When the electric field across the tunnel dielectric layer
13
is high, tunnel current becomes larger, and erase time becomes shorter, but a high electric field places excessive stress on a tunnel dielectric layer, causing damage and bringing about degradation or destruction. Therefore, there is a limit for high electric field to be placed on a tunnel dielectric layer.
Accordingly, in the past, there was proposed a variable erase voltage system, in which the voltage applied to a control gate during an erase operation is set low at the initial stage of erase, and is increased in line with the progress of the erase operation. According to this system, for example, a voltage of approximately −6 V is applied to the control gate at the start of erase operation, and as erasure progresses, the control gate voltage is lowered to −10 V. In this manner, the electric field being applied to the tunnel dielectric layer can be maintained constant to a certain degree, making it possible to prevent the applying of an excessive electric field to the tunnel dielectric layer, and to curb the degradation or destruction of the tunnel dielectric layer.
However, a conventional variable erase voltage system uniformly changes the erase voltage applied between a control gate and a substrate in accordance with erase time, or more specifically, with the number of erase pulses. For example, at the stage of designing a memory, an optimum erase voltage rise curve is determined for a number of erase pulses, and the erase voltage rise curve thereof is applied to all memory devices. As a result thereof, when erase speed differs from the design value due to production irregularities, either the electric field applied to the tunnel dielectric layer is too low and erase time becomes prolonged, or the applied electric field is too high and causes the degradation of the tunnel dielectric layer.
For example, as a typical example of a production irregularity, there is the variation in the thickness of a tunnel dielectric layer. When a tunnel dielectric layer becomes thick, the erase speed for the same control gate voltage slows down. In the case thereof, until the erase voltage is increased after a certain amount of erase time has elapsed, and, consequently, the electric field applied to the tunnel dielectric layer becomes higher, not much erasing is done, and actual erase time becomes longer than the set erase time.
By contrast, when a tunnel dielectric layer becomes thin, the erase speed for the same control gate voltage increases. In this case, because an excessive electric field is continuously applied to the tunnel dielectric layer, the degradation of the tunnel dielectric layer occurs. In particular, when the erase voltage is uniformly raised in accordance with erase time, such an excessive electric field becomes even more prominent.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an optimum variable erase voltage system for a memory for which erase speed fluctuates in accordance with production irregularities.
Further, another object of the present invention is to provide a semiconductor nonvolatile memory for optimally controlling changes in erase voltage corresponding to changes in erase speed resulting from production irregularities.
To achieve the above-mentioned objects, the present invention provides
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Phan Trong
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