Semiconductor device and fabrication process therefor

Details Semiconductor device and fabrication process therefor Semiconductor device and fabrication process therefor

2000-12-01

2002-07-09

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S758000, C257S786000

Reexamination Certificate

active

06417575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a fabrication process therefor and particularly, to a semiconductor device having a structure of a pad electrode used as an electrode to connect a semiconductor element on a semiconductor substrate to an external terminal and a fabrication process therefor.
2. Description of the Background Art
In a semiconductor device, wiring made of copper (Cu) as a main ingredient with lower resistivity and higher reliability has been adopted instead of conventional wiring made of aluminum (Al) as a main ingredient for purposes of reduction in wiring delay (reduction in wiring resistance) and increase in a wiring allowable current density such that a high speed operation and high performance of the device are realized.
A pad electrode is generally formed using a metal wiring in the uppermost layer simultaneously with when the wiring is formed, and a wire is directly bonded to the pad electrode for connection to an external terminal by means of a wire bonding method, or alternatively with a flip-chip mounting method, after a connection electrode such as a bump electrode is formed, connection is made from the pad electrode to an external terminal through the connection electrode. Since copper in use as wiring material is poor in adaptation to microfabrication in dry etching, a buried wiring (Damascene) technique adopting a chemical mechanical polishing (CMP) process has mainly employed in formation of an wiring. Therefore, a bonding pad electrode is also generally formed using the buried wiring method.
FIGS. 122A and 122B
, show an example of a sectional structure of a conventional semiconductor device using such a copper wiring.
As shown in
FIG. 122B
, on a semiconductor substrate
1
, an element isolation insulating film
2
, a gate insulating film
3
, a gate electrode
4
and an impurity diffused layer
5
are formed to construct a MOS (metal oxide semiconductor) transistor
6
. A bottom insulating film
7
is formed on the MOS transistor
6
and a contact hole
8
is formed in the bottom insulating film
7
so as to penetrate through the bottom insulating film
7
from a first metal (W) wiring layer
10
including a first wiring trench
9
downward. A first interlayer insulating film
11
is further formed on the bottom insulating film
7
and a first via hole
12
is formed in the first interlayer insulating film
11
so as to penetrate through the first interlayer insulating film
11
from a second metal (Cu) wiring layer
14
including a second wiring trench
13
downward. A second interlayer insulating film
15
is formed on the first interlayer insulating film
11
and a second via hole
16
is still further formed in the second interlayer insulating film
15
so as to penetrate through the second interlayer insulating film
15
from a third metal (Cu) wiring layer
18
including a third wiring trench
17
downward. Part of the third metal (Cu) wiring layer
18
serves as a pad electrode
19
. While on the second interlayer insulating film
15
, a protective insulating film
20
and a buffer coat film
21
are formed to cover the second interlayer insulating film
15
, the pad electrode
19
is exposed in a pad electrode opening
22
at a site corresponding to the electrode
19
.
Description will be given of a fabrication process for a conventional semiconductor device shown in
FIGS. 122A and 122B
with reference to
FIGS. 123
to
132
.
In this example, an wiring layer has a three-layer metal wiring structure stacked with a tungsten (W) wiring and two copper layers, and a pad electrode is formed with a copper wiring in the uppermost layer. Please note that in this case, a process called Dual Damascene process is adopted as example, in which each metal wiring layer has a connection hole and an wiring trench formed in advance and after the hole or the trench is filled with a metal film, unnecessary portions of the metal film are removed by chemical mechanical polishing (CMP) process.
As shown in
FIG. 123
, on a semiconductor substrate
1
, fabricated is a semiconductor element
6
such as a MOS transistor composed of an element isolation insulating film
2
, a gate insulating film
3
, a gate electrode
4
and an impurity diffused layer
5
. Then, bottom insulating film
7
of a three-layer structure is formed over all the surface of the semiconductor element
6
by stacking sequentially films to be included in the bottom insulating film
7
: a silicon oxide film (SiO), an insulating film
7
a
made of a silicon oxide film or the like including impurity such as phosphorus (P) or boron (B); a silicon nitride film (SiN)
7
b
as an etching stopper layer used in wiring trench processing, and an insulating film
7
c
such as a silicon oxide film (SiO) for forming an wiring trench therein by means of a method such as a thermal CVD (Chemical Vapor Deposition) method, a plasma CVD method or the like.
As shown in
FIG. 124
, a contact hole
8
and a first wiring trench
9
are formed in the bottom insulating film
7
at a desired site thereon using photolithography and an etching technique. At this time, the silicon nitride film (SiN)
7
b
works as a stopper film when the first wiring trench
9
is processed since a etching selectivity to the silicon oxide film
7
c
is higher than that to the silicon nitride (SiN)
7
b.
As shown in
FIG. 125
, a barrier metal film
10
a
and a tungsten (W) film
10
b
are deposited over all the surface such that the contact hole
8
and the first wiring trench
9
are filled with the films
10
a
and
10
b
. As the barrier metal film
10
a
, for example, a stacked layer including a titanium (Ti) film of 5 to 50 nm thick and a titanium nitride film (TiN) film of 10 to 100 nm thick is employed in order to attain a good ohmic contact with the impurity diffused layer
5
of the semiconductor element
6
and the stacked layer is deposited by a PVD (Physical Vapor Deposition) method or a CVD method. On the other hand, the tungsten (W) film
10
b
is deposited by a thermal CVD method using a reduction reaction between tungsten hexafluoride (WFG) and hydrogen (H
2
).
As shown in
FIG. 126
, the tungsten film
10
b
and the barrier metal (TiN/Ti) film
10
a
other than those in the contact hole
8
and the first wiring trench
9
are removed by means of, for example, a chemical mechanical polishing (CMP) process using an alumina polishing agent with hydrogen peroxide (H
2
O
2
) as a base to form a first buried metal (W) wiring layer
10
. A thickness of the tungsten wiring layer
10
generally ranges approximately from 100 to 300 nm.
As shown in
FIG. 127
, on the first metal (W) wiring layer
10
, a first interlayer insulating film
11
of a three-layer structure is formed by stacking sequentially films to be included in the first interlayer insulating film
11
: an insulating film
11
a
such as silicon oxide film (SiO), a silicon nitride film (SiN)
11
b
and an insulating film
11
c
such as a silicon oxide film (SiO) using a plasma CVD method or the like. Moreover, photolithography and an etching technique are adopted to form a first via hole
12
and a second wiring trench
13
in the first interlayer insulating film
11
at a desired site thereon
As shown in
FIG. 128
, an underlying film
14
a
and copper (Cu) films
14
b
and
14
c
are deposited over all the surface such that the first via hole
12
and the second interconnect trench
13
are filled with the films
14
a
,
14
b
and
14
c
. The underlying film
14
a
has a function to prevent copper (Cu) from diffusing into a silicon oxide film or the like adjacent to the copper (Cu) films
14
b
and
14
c
and is generally formed by stacking a tantalum (Ta) film, a Tantalum nitride (TaN) film, a stacked film of tantalum and tantalum nitride (TaN/Ta), a Titanium nitride (TiN) film, or a stacked film of titanium and titanium nitride (TiN/Ti) to a thickness approximately in the range of 10 to 100 nm using a PVD method or a CVD method. Then, a copper seed film
14
b
as an underlying film for elect

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