Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-14
2002-05-28
Le, N. (Department: 2815)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C438S008000, C438S016000, C438S017000, C438S018000, C438S024000, 43
Reexamination Certificate
active
06396297
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.
BACKGROUND OF THE INVENTION
In the context of document processing, a raster input scanner, or simply “scanner,” is a device by which an image on a hardcopy original, such as a sheet of paper, is converted to digital data. A common design for a scanner includes a linear array of photosites with corresponding circuitry to form a linear array of photosensors. Each photosensor in the array is adapted to output a signal, typically in the form of an electrical charge or voltage, of a magnitude proportional to or otherwise related to the intensity of light incident on the photosensor. By providing a linear array of these photosensors and causing the array to scan relative to the hard-copy original, each photosensor will output a sequence of charge signals resulting from the various gradations of dark and light in the image as the individual photosensors move through a path relative to an image.
In most low cost scanners, such as presently found in inexpensive facsimile machines, the most typical technology for creating such a scanner is the charge-coupled device, or CCD. For higher-quality applications, CMOS technology in one or more photosensor chips are used.
The number of photosites (and therefore photosensors) that can be packed onto a single chip or wafer is limited, and this, in turn, limits the image resolution that can be achieved with a single photosensitive array. Joining several of the smaller photosensor arrays together to form a longer array, and particularly, to form a full page width array with increased resolution along with the attendant simplification of the scanning system that this allows is desirable.
Arrays of photosites are typically formed from a plurality of generally rectangular substrates and these substrates are separated by dicing or other suitable means from one or more circular silicon wafers to form photosensitive chips. (The shape of substrates do not have to be rectangular. Other geometric shapes are also possible). The photosensitive chips are preferably assembled end to end in a collinear fashion to improve image quality and to form a full width array.
One method presently employed to produce photosensitive chips is the formation of aligned V-grooves in the semiconductor wafer. The V-grooves are preferably etched along the 111 plane of the silicon, which is the easy slip plane for stress relief or cracks. V-grooves are needed for proper dicing of the chips in regions very close to active circuits. If the proper V-groove width is not there for each chip during dicing, chipping damage may occur and this will cause yield problems or a reliability degradation problem in the final photosensor array. Only 100% visual inspection of all wafers catches all of these defects, or a 100% visual inspection of a sample of wafers might indicate that there is a problem. Visual inspection of every chip on every wafer is labor intensive and prone to human error. Therefore, there is a need for a new method and apparatus to inspect and evaluate V-groove widths on the semiconductor wafer.
SUMMARY OF THE INVENTION
The present invention provides an apparatus for detecting width of a V-groove on a semiconductor wafer including a V-groove width monitor resistor overlapping a chip area and an area upon which the V-groove is to be etched; an pad etched on the silicon wafer and coupled to the V-groove width monitor resistor; and a tester supplying voltage to the pad after the V-groove has been etched into the silicon wafer; and apparatus to determine the width of the etched V-groove. The pad can be an input/output pad. The pad can be a separate test pad for testing V-groove width only. A pull up resistance may be connected to the pad and V-groove width monitor resistor.
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Browne Paul W.
Hosier Paul A.
TeWinkle Scott L.
Daebeler P.
Hamdan Wasseem H.
Le N.
Xerox Corporation
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