Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2000-06-21
2002-05-07
Ngô, Ngâ V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S204000, C257S206000
Reexamination Certificate
active
06384434
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device having at least two types of output cells including an output cell with high driving capability and an output cell with low driving capability.
2. Description of Background Art
In a semiconductor integrated circuit such as a gate array device or an embedded array device, driving capability required for each input/output cell may be different. In the input/output cells for which high driving capability is required, large transistors must be used for the output driver. When such large transistors are used in the input/output cells for which low driving capability is required, noises such as overshoots or undershoots increase when the signal changes. Driving capability can be restrained by connecting a diffusion resistor in series to the output line of the large transistors. However, this requires an area for forming the diffusion resistor, thereby increasing the area for the input/output cells. Moreover, this causes rising or falling characteristics of the signals to deteriorate. Therefore, small transistors have been used for output drivers in input/output cells for which low driving capability is required to achieve the required driving capability.
In the case of full-custom semiconductor devices, driving capability of each input/output cell has been determined when manufacturing a bulk substrate. Therefore, transistors with the required sizes are fabricated in each input/output cell.
However, in the case of master-slice semiconductor devices in which a lot of transistors is fabricated in a bulk substrate in advance, wiring of the lot of transistors is determined afterward according to the logic and capabilities required by the customer. This applies not only to the internal cell region positioned at the center of the semiconductor device, but also to the input/output cells disposed around the internal cell region.
Therefore, for master-slice semiconductor devices, a plurality of transistors with a large gate width and at least one transistor with a small gate width must be previously placed in each input/output cell. High driving capability can be obtained by connecting the transistors with a large gate width in parallel. By using only the transistor with a small gate width, driving capability smaller than the driving capability obtained by using one transistor with a large gate width can be obtained.
However, conventional master-slice semiconductor devices need two or more types of transistors with different gate widths according to the driving capability required for each input/output cell to be fabricated. This increases the area required for each input/output cell as well as cost due to the complicated design.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing cost by downsizing input/output cells, thereby reducing the chip area when the driving capability required for each input/output cell differs.
One aspect of the present invention provides a master-slice semiconductor device in which a lot of transistors are formed on a semiconductor substrate, transistors selected from the lot of transistors being connected by wiring, the master-slice semiconductor device comprising an input/output cell region disposed in a peripheral part of the semiconductor device and an internal cell region disposed inside the input/output cell region. A plurality of output cells are disposed in the input/output cell region. An output terminal and a plurality of transistors are disposed in each of output cells, with at least one transistor selected from the plurality of transistors being connected to the output terminal. Each of the plurality of transistors comprises: a gate electrode formed on the semiconductor substrate through a gate-insulating film; and two diffusion regions formed at the semiconductor substrate on both sides of the gate electrode. And one of the diffusion regions of at least one of the plurality of transistors is divided into a plurality of divisional diffusion regions in a direction of the width of the gate electrode.
According to this aspect of the present invention, by separating the impurity diffusion region into a plurality of divisional diffusion regions, the transistor can be divided to correspond to each of the divisional diffusion regions. The gate width of the transistor, including a divisional diffusion region, is less than that of other transistors including the diffusion regions which are not divided. Therefore, an output driver with low current driving capability can be constituted by using a transistor with a small gate width. The transistors with the divided impurity-diffusion region can be made to have the same current driving capability as other transistors by using the divisional diffusion regions together as a common drain. Therefore, an output driver with higher current driving capability can be constituted by connecting two or more transistors in parallel.
By thus dividing an impurity-diffusion region, the transistor with the divisional diffusion region can be used as a transistor with a small gate width or a transistor with a standard gate width. It is therefore unnecessary to separately form a transistor with a small gate width. Consequently, an area for input/output cells, and hence the chip area can be reduced.
An element isolation region may be disposed between the adjacent divisional diffusion regions. The divisional diffusion regions are thereby separated.
The other of the diffusion regions on both sides of the gate electrode may have a region divided by the element isolation region at a portion near the gate electrode. A region other than the divided region may be continuous in the direction of the gate width. This prevents charge transfer between adjacent divisional diffusion regions. Moreover, a part continuous in the direction of the gate width can be left in the other diffusion region. Since this region is used as a common source by wiring, it is unnecessary to divide this region completely. The element isolation region may be formed of an element isolating insulation film.
It is preferable that the gate electrode of each of the plurality of transistors is disposed in parallel, and impurity-diffusion regions between two gate electrodes are used as one of a common source and a common drain of two transistors. By this configuration, a plurality of transistors can be disposed closely, thereby reducing the area for the output cells. The plurality of divisional diffusion regions are preferably formed in an endmost impurity diffusion region. This is because only the transistor with the gate electrode at the end can be divided into a plurality of transistors. However, not only the endmost impurity-diffusion region but also the region between any two parallel gate electrodes may be divided. In this case, two transistors consisting of two gate electrodes and the impurity-diffusion regions on both sides thereof are divided.
One of the divisional diffusion regions having the smallest width may form a transistor having the smallest current driving capability together with the electrode and the other of the diffusion regions. Therefore, an output transistor with the smallest driving capability can be constituted by using only this transistor.
The widths of the each of the divisional diffusion regions may be the same or different.
At least one of the divisional diffusion regions in at least one of the output cells may be a drain region to be connected to the output terminal by wiring. By using the divisional diffusion region as the drain, the transistor can be used as an output driver.
Each of the output cells may comprise: a first output driver disposed between the output terminal and a VDD potential supply line; and a second output driver disposed between the output terminal and a VSS potential supply line. The first output driver may be formed by wiring at least one transistor selected from a plurality of p-type transistors.
Ngô Ngâ V.
Seiko Epson Corporation
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