Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2001-01-17
2002-04-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S052000, C365S063000
Reexamination Certificate
active
06370053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a high-speed memory address driver circuit. More particularly, the present invention relates to an address driver circuit for driving the dynamic random access memory on a computer main board.
2. Description of Related Art
Most personal computer system consists of a main board, interface cards and peripheral devices. The main computer board is the heart of a computer system. Besides having a central processing unit (CPU), a control chipset and a few slots for plugging interface cards, the main computer board also includes a plurality of memory module slots. The number of memory modules inserted into the slots depends on user's need. In general, each memory module consists of a few memory units. Nowadays, most personal computers have total internal memory from a few tens of megabytes to several hundreds of megabytes.
The memory used inside most personal computers, such as synchronous dynamic access memory (SDRAM), transfers data in response to the rising edge of a clock pulse signal. However, there is another type of memory called double-data-rate dynamic random access memory (DDR DRAM). The DDR DRAM has double data transfer rate because the memory transfers data in response to both the rising edge and falling edge of a clock pulse signal.
At present, both SDRAM and DDR DRAM modules are developed in parallel. Due to considerations such as marketing, administration, production cost, compatibility and expandability, main board that can support both SDRAM and DDR DRAM memory modules is in great demand. However, on a main board, the bus for operating SDRAM modules and the bus for operating DDR DRAM must be designed differently because of some fundamental differences in operation between the modules. The bus for operating SDRAM modules does not require pull-up resistors or terminal resistors. On the other hand, the data bus for operating DDR DRAM modules must connect with pull-up resistors. If the control chipset includes two groups of address circuits for supporting DDR DRAM modules, layout in the main board must incorporate two groups of terminal resistor circuits. Due to an increase area occupation of the resistor circuits on the board surface and the cost for fabricating the additional resistor circuits, production cost will increase and layout design will be more difficult.
Rapid development of semiconductor technologies has increased the processing power of CPU. Most personal computers now operate with a clocking frequency up to several hundred MHz. Following the rapid increase in clocking rate of CPU, clocking frequency of memory units must also increase to 100 MHz or above. In high-speed operation, since both conventional SDRAM and DDR DRAM use a memory access command timing of two cycles (2T), actual operating speed of the system is reduced considerably from what is potentially possible. This is especially true for a computer system having DDR DRAM modules. Hence, system performance will improve considerably if common one cycle (1T) access command timing is used in accessing module memory.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a memory address driver circuit capable of using the common one cycle (1T) timing of a computer system for accessing data in memory modules, thereby improving system performance. In addition, engineers have to design a group of terminal resistors only, thereby saving production cost.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a memory address driver circuit. The memory address driver circuit includes a first memory module slot having a plurality of address leads, a second memory module slot having a plurality of address leads, a control chipset and a plurality of terminal resistors. A first memory module can be plugged into the first memory module slot and a second memory module can be plugged into the second memory module slot. The control chipset includes a first memory control circuit and a second memory control circuit. The first memory control circuit controls the transmission of data to and from any first memory module already plugged in the first memory module slot. Similarly, the second memory control circuit controls the transmission of data to and from any second memory module already plugged in the second memory module slot. The first memory control circuit and the second memory control circuit each has an independent group of address leads. The address leads of the first memory control circuit connect with corresponding address leads of the first memory module slot while the address leads of the second memory control circuit connect with corresponding address leads of the second memory module slot. The first memory module slot is closer to other memory module slots. Furthermore, the address leads of the first memory module slot do not connect with any terminal resistors.
According to one preferred embodiment of this invention, the first memory module is a double-data-rate dynamic random access memory module. When the first memory module is plugged into the first memory module slot, the first memory control circuit uses a first memory command timing (1T memory command timing) to access the first memory module. When a second memory module is plugged into the second memory module slot, the second memory control circuit uses a second memory command timing (2T memory command timing) to access the second memory module. In this invention, there are two groups of memory control circuits with one group using a faster 1T timing. Since address lines of common memory modules are all connected to the faster 1T control circuit, performance of the computer system will improve considerably. In addition, engineers do not have to design two groups of terminal resistors because only one memory address driver requires terminal resistors. Hence, design of terminal resistor is simplified without compromising system stability.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5490118 (1996-02-01), Nishioka et al.
patent: 5953243 (1999-09-01), Capps, Jr. et al.
patent: 6253284 (2001-06-01), Hsu
patent: 6260105 (2001-07-01), Williams et al.
Chang Nai-Shung
Chen Chia-Hsin
J.C. Patents
Phan Trong
Via Technologies Inc.
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